DS90LV110T_14 Datasheet, PDF (6/17 Pages) Texas Instruments – 1 to 10 LVDS Data/Clock Distributor

DS90LV110T
SNOS522I – JANUARY 2001 – REVISED APRIL 2013
www.ti.com
Figure 7. Output 1 to 10 Channel-to-Channel Skew
APPLICATION INFORMATION
Input Fail-Safe
The receiver inputs of the DS90LV110 do not have internal fail-safe biasing. For point-to-point and multi-drop
applications with a single source, fail-safe biasing may not be required. When the driver is off, the link is in-
active. If fail-safe biasing is required, this can be accomplished with external high value resistors. The IN+ should
be pull to Vcc with 10kΩ and the IN− should be pull to Gnd with 10kΩ. This provides a slight positive differential
bias, and sets a known HIGH state on the link with a minimum amount of distortion. See AN-1194(SNLA051) for
additional information.
LVDS Inputs Termination
The LVDS Receiver input must have a 100Ω termination resistor placed as close as possible across the input
pins.
Unused Control Inputs
The EN control input pin has internal pull down device. If left open, the 10 outputs will default to TRI-STATE.
Expanding the Number of Output Ports
To expand the number of output ports, more than one DS90LV110 can be used. Total propagation delay through
the devices should be considered to determine the maximum expansion. Adding more devices will increase the
output jitter due to each pass.
PCB Layout and Power System Bypass
Circuit board layout and stack-up for the DS90LV110 should be designed to provide noise-free power to the
device. Good layout practice also will separate high frequency or high level inputs and outputs to minimize
unwanted stray noise pickup, feedback and interference. Power system performance may be greatly improved by
using thin dielectrics (4 to 10 mils) for power/ground sandwiches. This increases the intrinsic capacitance of the
PCB power system which improves power supply filtering, especially at high frequencies, and makes the value
and placement of external bypass capacitors less critical. External bypass capacitors should include both RF
ceramic and tantalum electrolytic types. RF capacitors may use values in the range 0.01 µF to 0.1 µF. Tantalum
capacitors may be in the range 2.2 µF to 10 µF. Voltage rating for tantalum capacitors should be at least 5X the
power supply voltage being used. It is recommended practice to use two vias at each power pin of the
DS90LV110 as well as all RF bypass capacitor terminals. Dual vias reduce the interconnect inductance by up to
half, thereby reducing interconnect inductance and extending the effective frequency range of the bypass
components.
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