DS90LV110AT_14 Datasheet, PDF (8/17 Pages) Texas Instruments – 1 to 10 LVDS Data/Clock Distributor with Failsafe

DS90LV110AT
SNOSAC2J – AUGUST 2004 – REVISED APRIL 2013
www.ti.com
OUTPUT INTERFACING
The DS90LV110A outputs signals that are compliant to the LVDS standard. Their outputs can be DC-coupled to
most common differential receivers. Figure 10 illustrates typical DC-coupled interface to common differential
receivers and assumes that the receivers have high impedance inputs. While most differential receivers have a
common mode input range that can accommodate LVDS compliant signals, it is recommended to check
respective receiver's data sheet prior to implementing the suggested interface implementation.
DS90LV110A
Driver
OUT+
OUT-
100: Differential T-Line
Differential
Receiver
IN+
CML or
100:
LVPECL or
LVDS
IN-
Figure 10. Typical DS90LV110A Output DC-Coupled Interface to an LVDS, CML or LVPECL Receiver
Pin Name
IN+
IN -
OUT+
OUT -
EN
V_SS
V_DD
# of Pin
1
1
10
10
1
3
2
DS90LV110A PIN DESCRIPTIONS
Input/Output
Description
I
Non-inverting LVDS input
I
Inverting LVDS input
O
Non-inverting LVDS Output
O
Inverting LVDS Output
I
This pin has an internal pull-down when left open. A logic low on the
Enable puts all the LVDS outputs into TRI-STATE and reduces the
supply current.
P
Ground (all ground pins must be tied to the same supply)
P
Power Supply (all power pins must be tied to the same supply)
8
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