DS90LV110AT_14 Datasheet, PDF (7/17 Pages) Texas Instruments – 1 to 10 LVDS Data/Clock Distributor with Failsafe

DS90LV110AT
www.ti.com
SNOSAC2J – AUGUST 2004 – REVISED APRIL 2013
There are more common practices which should be followed when designing PCBs for LVDS signaling. Please
see Application Note: AN-1108(SNLA008) for additional information.
INPUT INTERFACING
The DS90LV110A accepts differential signals and allow simple AC or DC coupling. With a wide common mode
range, the DS90LV110A can be DC-coupled with all common differential drivers (that is, LVPECL, LVDS, CML).
Figure 7, Figure 8, and Figure 9 illustrate typical DC-coupled interface to common differential drivers.
LVDS
Driver
OUT+
100: Differential T-Line
DS90LV110A
Receiver
IN+
100:
OUT-
IN-
Figure 7. Typical LVDS Driver DC-Coupled Interface to DS90LV110A Input
CML3.3V or CML2.5V
Driver
V_CC
50:
50:
OUT+
100: Differential T-Line
DS90LV110A
Receiver
IN+
100:
OUT-
IN-
Figure 8. Typical CML Driver DC-Coupled Interface to DS90LV110A Input
LVPECL
Driver
OUT+
OUT-
50:
100: Differential T-Line
DS90LV110A
Receiver
IN+
100:
IN-
50:
Figure 9. Typical LVPECL Driver DC-Coupled Interface to DS90LV110A Input
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