DS90LV110AT_14 Datasheet, PDF (1/17 Pages) Texas Instruments – 1 to 10 LVDS Data/Clock Distributor with Failsafe

DS90LV110AT
www.ti.com
SNOSAC2J – AUGUST 2004 – REVISED APRIL 2013
DS90LV110AT 1 to 10 LVDS Data/Clock Distributor with Failsafe
Check for Samples: DS90LV110AT
FEATURES
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•2 Low jitter 400 Mbps fully differential data path
• 145 ps (typ) of pk-pk jitter with PRBS = 2²³âˆ’1
data pattern at 400 Mbps
• Single +3.3 V Supply
• Balanced output impedance
• Output channel-to-channel skew is 35ps (typ)
• Differential output voltage (V_OD) is 320mV (typ)
with 100Ω termination load.
• LVDS receiver inputs accept LVPECL signals
• LVDS input failsafe
• Fast propagation delay of 2.8 ns (typ)
• Receiver open, shorted, and terminated input
failsafe
• 28 lead TSSOP package
• Conforms to ANSI/TIA/EIA-644 LVDS standard
DESCRIPTION
DS90LV110A is a 1 to 10 data/clock distributor
utilizing LVDS (Low Voltage Differential Signaling)
technology for low power, high speed operation. Data
paths are fully differential from input to output for low
noise generation and low pulse width distortion. The
design allows connection of 1 input to all 10 outputs.
LVDS I/O enable high speed data transmission for
point-to-point interconnects. This device can be used
as a high speed differential 1 to 10 signal distribution
/ fanout replacing multi-drop bus applications for
higher speed links with improved signal quality. It can
also be used for clock distribution up to 200MHz.
The DS90LV110A accepts LVDS signal levels,
LVPECL levels directly or PECL with attenuation
networks.
The LVDS outputs can be put into TRI-STATE by use
of the enable pin.
For more details, please refer to the APPLICATION
INFORMATION section of this datasheet.
Connection Diagram
Order Number DS90LV110ATMT
PW0028A Package
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2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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