DS90LV110AT_14 Datasheet, PDF (4/17 Pages) Texas Instruments – 1 to 10 LVDS Data/Clock Distributor with Failsafe

DS90LV110AT
SNOSAC2J – AUGUST 2004 – REVISED APRIL 2013
www.ti.com
AC Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
T_LHT
T_HLT
T_DJ
T_RJ
T_PLHD
T_PHLD
T_SKEW
T_CCS
T_PHZ
T_PLZ
T_PZH
T_PZL
Parameter
Conditions
Output Low-to-High Transition Time, 20% to 80%, Figure 4 ⁽¹⁾
Output High-to-Low Transition Time, 80% to 20%, Figure 4 ⁽¹⁾
LVDS Data Jitter, Deterministic (Peak-to-
Peak) ⁽²⁾
LVDS Clock Jitter, Random ⁽²⁾
V_ID = 300mV; PRBS=2²³-1 data;
V_CM = 1.2V at 400 Mbps (NRZ)
V_ID = 300mV;
V_CM = 1.2V at 200 MHz clock
Propagation Low to High Delay, Figure 5
Propagation High to Low Delay, Figure 5
Pulse Skew |T_PLHD - T_PHLD| ⁽¹⁾
Output Channel-to-Channel Skew, Figure 6 ⁽¹⁾
Disable Time (Active to TRI-STATE) High to Z, Figure 1
Disable Time (Active to TRI-STATE) Low to Z, Figure 1
Enable Time (TRI-STATE to Active) Z to High, Figure 1
Enable Time (TRI-STATE to Active) Z to Low, Figure 1
Min
Typ
Max Units
390
550
ps
390
550
ps
145
ps
2.8
ps
2.2
2.8
3.6
ns
2.2
2.8
3.9
ns
20
340
ps
35
91
ps
3.0
6.0
ns
1.8
6.0
ns
10.0 23.0
ns
7.0
23.0
ns
(1) The parameters are specified by design. The limits are based on statistical analysis of the device performance over PVT (process,
voltage and temperature) range.
(2) The measurement used the following equipment and test setup: HP8133A pattern/pulse generator), 5 feet of RG-142 cable with DUT
test board and HP83480A (digital scope mainframe) with HP83484A (50GHz scope module). The HP8133A with the RG-142 cable
exhibit a T_DJ = 26ps and T_RJ = 1.3 ps
AC TIMING DIAGRAMS
Figure 1. Output active to TRI-STATE and TRI-STATE to active output time
4
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