CD74HC652_15 Datasheet, PDF (8/13 Pages) Texas Instruments – High-Speed CMOS Logic Octal-Bus Transceiver/Registers, Three-State

CD74HC652, CD74HCT652
Test Circuits and Waveforms
t_rC_L
CLOCK
90%
10%
t_fC_L
50%
10%
t_WL
t_WL
+
t_WH
=
I
fC_L
50%
50%
t_WH
V_CC
GND
t_rC_L = 6ns
CLOCK
2.7V
0.3V
t_fC_L = 6ns
t_WL
+
t_WH
=
I
fC_L
3V
1.3V
0.3V
1.3V
1.3V
GND
t_WL
t_WH
NOTE: Outputs should be switching from 10% V_CC to 90% V_CC in
accordance with device truth table. For f_MAX, input duty cycle = 50%.
FIGURE 2. HC CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH
NOTE: Outputs should be switching from 10% V_CC to 90% V_CC in
accordance with device truth table. For f_MAX, input duty cycle = 50%.
FIGURE 3. HCT CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH
t_r = 6ns
INPUT
90%
50%
10%
t_f = 6ns
V_CC
GND
t_THL
INVERTING
OUTPUT
t_PHL
t_TLH
90%
50%
10%
t_PLH
FIGURE 4. HC TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
t_r = 6ns
INPUT
t_THL
2.7V
1.3V
0.3V
INVERTING
OUTPUT
t_PHL
t_f = 6ns
3V
GND
t_TLH
90%
1.3V
10%
t_PLH
FIGURE 5. HCT TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
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