CD74HC652_15 Datasheet, PDF (1/13 Pages) Texas Instruments – High-Speed CMOS Logic Octal-Bus Transceiver/Registers, Three-State

Data sheet acquired from Harris Semiconductor
SCHS194A
February 1998 - Revised May 2003
CD74HC652,
CD74HCT652
High-Speed CMOS Logic
Octal-Bus Transceiver/Registers, Three-State
Features
Description
• CD74HC652, CD74HCT652 . . . . . . . . . . . Non-Inverting
[^• /^IT^ndit^ele^pe(ⁿC^dD^en7^t4^RH^egC^is6^t5^e2^rs, ^fC^orD^A74^anH^dC^BT^B6^u5^s2^e)^s
/•STuhbrjeeec-tS(taHteigOhu-tSppuetsed CMOS Logic Octal-Bus
T_• r_Da_rn_ivs_ec_sei₁v₅e_Lr/_SR_Te_Tg_Lis_Lt_oe_ar_ds_s, Three-State)
/Author ()
/^•K^Te^yy^pw^icao^lr^Pd^rs^op()^{agation Delay = 12ns at VCC = 5V, CL = 15pF}
/^•C^Fr^aeⁿa^oto^ur^{t (}(^O) ^{ver Temperature Range)}
/D^-O^SC^taIⁿN^dF^aO^{rd O}pd^uf^tpm^ua^tsrk^{. . . . . . . . . . . . . . . 10 LSTTL Loads}
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
[^• /^WPa^idg^ee^OM^po^erd^ae^tin/^gU^Ts^ee^mO^pu^et^rl^ai^tn^ue^rs^{e Range . . . -55oC to 125oC}
/•DBOalCanVcIeEdWProppdafgmataiorkn Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• Alternate Source is Philips
• HC Types
- 2V to 6V Operation
- High Noise Immunity: N_IL = 30%, N_IH = 30% of V_CC
at V_CC = 5V
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V_IL= 0.8V (Max), V_IH = 2V (Min)
- CMOS Input Compatibility, I_l ≤ 1µA at V_OL, V_OH
The CD74HC652 and CD74HCT652 three-state, octal-bus
transceiver/registers use silicon-gate CMOS technology to
achieve operating speeds similar to LSTTL with the low power
consumption of standard CMOS integrated circuits. The
CD74HC652 and CD74HCT652 have non-inverting outputs.
These devices consists of bus transceiver circuits, D-type flip-
flops, and control circuitry arranged for multiplexed
transmission of data directly from the data bus or from the
internal storage registers. Output Enables OE_AB and OE_BA
are provided to control the transceiver functions. SAB and
SBA control pins are provided to select whether real-time or
stored data is transferred. The circuitry used for select control
will eliminate the typical decoding glitch that occurs in a
multiplexer during the transition between stored and real-time
data. A LOW input level selects real-time data, and a HIGH
selects stored data. The following examples demonstrates the
four fundamentals bus-management functions that can be
performed with the octal-bus transceivers and registers.
Data on the A or B data bus, or both, can be stored in the
internal D flip-flops by low-to-high transitions at the appropriate
clock pins (CAB or CBA) regardless of the select of the control
pins. When SAB and SBA are in the real-time transfer mode, it
is also possible to store data without using the D-type flip-flops
by simultaneously enabling OE_AB and OE_BA. In this
configuration, each output reinforces its input. Thus, when all
other data sources to the two sets of bus lines are at high
impedance, each set of bus lines will remain at its last state.
Ordering Information
Pinout
CD74HC652
(PDIP)
CD74HCT652
( SOIC)
TOP VIEW
CAB 1
SAB 2
OE_AB 3
A0 4
A1 5
A2 6
A3 7
A4 8
A5 9
A6 10
A7 11
GND 12
24 V_CC
23 CBA
22 SBA
21 OE_BA
20 B0
19 B1
18 B2
17 B3
16 B4
15 B5
14 B6
13 B7
PART NUMBER
TEMP. RANGE
(^oC)
PACKAGE
CD74HC652EN
-55 to 125
24 Ld PDIP
CD74HCT652M
-55 to 125
24 Ld SOIC
CD74HCT652M96
-55 to 125
24 Ld SOIC
NOTE: When ordering, use the entire part number. The suffix 96
denotes tape and reel.
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2003, Texas Instruments Incorporated
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