BQ4285_14 Datasheet, PDF (8/29 Pages) Texas Instruments – Real-Time Clock (RTC) With NVRAM Control

bq4285
Power-Down/Power-Up Cycle
The bq4285 continuously monitors VCC for out-of-
tolerance. During a power failure, when VCC falls below
VPFD (4.17V typical), the bq4285 write-protects the clock
and storage registers. When VCC is below VBC (3V typi-
cal), the power source is switched to BC. RTC operation
and storage data are sustained by a valid backup energy
source. When VCC is above VBC, the power source is
VCC. Write-protection continues for tCSR time after VCC
rises above VPFD.
An external CMOS static RAM is battery-backed using
the VOUT and chip enable output pins from the bq4285.
As the voltage input VCC slows down during a power
failure, the chip enable output, CEOUT, is forced inactive
independent of the chip enable input CEIN.
This activity unconditionally write-protects the external
SRAM as VCC falls below VPFD. If a memory access is in
process to the external SRAM during power-fail detec-
tion, that memory cycle continues to completion before
the memory is write-protected. If the memory cycle is
not terminated within time tWPT (30µs maximum), the
chip enable output is unconditionally driven high,
write-protecting the controlled SRAM.
As the supply continues to fall past VPFD, an internal
switching device forces VOUT to the external backup en-
ergy source. CEOUT is held high by the VOUT energy
source.
During power-up, VOUT is switched back to the 5V sup-
ply as VCC rises above the backup cell input voltage
sourcing VOUT. CEOUT is held inactive for time tCER
(200ms maximum) after the power supply has reached
VPFD, independent of the CEIN input, to allow for proces-
sor stabilization.
During power-valid operation, the CEIN input is passed
through to the CEOUT output with a propagation delay
of less than 10ns.
Figure 4 shows the hardware hookup for the external
RAM.
A primary backup energy source input is provided on
the bq4285. The BC input accepts a 3V primary battery,
typically some type of lithium chemistry. To prevent
battery drain when there is no valid data to retain,
VOUT and CEOUT are internally isolated from BC by the
initial connection of a battery. Following the first appli-
cation of VCC above VPFD, this isolation is broken, and
the backup cell provides power to VOUT and CEOUT for
the external SRAM.
Figure 4. External RAM Hookup to the bq4285 RTC
8