BQ4285_14 Datasheet, PDF (2/29 Pages) Texas Instruments – Real-Time Clock (RTC) With NVRAM Control

bq4285
Block Diagram
Pin Descriptions
AD0–AD7 Multiplexed address/data input/
output
The bq4285 bus cycle consists of two
phases: the address phase and the data-
transfer phase. The address phase pre-
cedes the data-transfer phase. During the
address phase, an address placed on
AD0–AD7 is latched into the bq4285 on the
falling edge of the AS signal. During the
data-transfer phase of the bus cycle, the
AD0–AD7 pins serve as a bidirectional data
bus.
MOT
Connect to VSS for correct operation
CS
Bus
Type
Chip select input
CS should be driven low and held stable
during the data-transfer phase of a bus cy-
cle accessing the bq4285.
Table 1. Bus Setup
MOT
DS
R/W
AS
Level Equivalent Equivalent Equivalent
Intel
VSS RD,
MEMR,
or I/OR
WR,
MEMW,
or I/OW
ALE
2