BQ4017_14 Datasheet, PDF (8/14 Pages) Texas Instruments – 2048Kx8 Nonvolatile SRAM

Not Recommended for new Designs
bq4017/bq4017Y
Power-Down/Power-Up Cycle (TA = 0 to 70°C)
Symbol
Parameter
tPF
VCC slew, 4.75 to 4.25 V
tFS
VCC slew, 4.25 to VSO
tPU
VCC slew, VSO to VPFD
(max.)
t
CER
Chip enable recovery time
tDR
tWPT
Data-retention time in
absence of V_CC
Write-protect time
Minimum
300
10
0
40
5
40
Typical
-
-
-
80
-
100
Maximum Unit
-
µs
-
µs
Conditions
-
µs
Time during which SRAM
120
ms
is write-protected after
VCC passes VFPD on
power-up.
-
years TA = 25°C. (2)
Delay after VCC slews
150
µs down past V_PFD before
SRAM is write-protected.
Notes: 1. Typical values indicate operation at TA = 25°C, VCC = 5V.
2. Batteries are disconnected from circuit until after VCC is applied for the first time. tDR is the
accumulated time in absence of power beginning when power is first applied to the device.
Caution: Negative undershoots below the absolute maximum rating of -0.3V in battery-backup mode
may affect data integrity.
Power-Down/Power-Up Timing
8