BQ4017_14 Datasheet, PDF (6/14 Pages) Texas Instruments – 2048Kx8 Nonvolatile SRAM

Not Recommended for new Designs
bq4017/bq4017Y
Write Cycle (TA = 0 to 70°C, VCCmin ≤ VCC ≤ VCCmax)
Symbol
Parameter
tWC
Write cycle time
tCW
Chip enable to end of write
tAW
Address valid to end of write
tAS
Address setup time
tWP
tWR1
tWR2
tDW
tDH1
tDH2
tWZ
tOW
Write pulse width
Write recovery time
(write cycle 1)
Write recovery time
(write cycle 2)
Data valid to end of write
Data hold time
(write cycle 1)
Data hold time
(write cycle 2)
Write enabled to output in high Z
Output active from end of write
-70
Min. Max.
70
-
65
-
65
-
0
-
55
-
5
-
15
-
30
-
0
-
10
-
0
25
5
-
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Conditions/Notes
(1)
(1)
Measured from address valid to be-
ginning of write. (2)
Measured from beginning of write to
end of write. (1)
Measured from WE going high to
end of write cycle. (3)
Measured from CE going high to
end of write cycle. (3)
Measured to first low-to-high transi-
tion of either CE or WE.
Measured from WE going high to
end of write cycle. (4)
Measured from CE going high to
end of write cycle. (4)
I/O pins are in output state. (5)
I/O pins are in output state. (5)
Notes:
1. A write ends at the earlier transition of CE going high and WE going high.
2. A write occurs during the overlap of a low CE and a low WE. A write begins at the later transition
of CE going low and WE going low.
3. Either tWR1 or tWR2 must be met.
4. Either tDH1 or tDH2 must be met.
5. If CE goes low simultaneously with WE going low or after WE going low, the outputs remain in
high-impedance state.
6