BQ24085_17 Datasheet, PDF (8/42 Pages) Texas Instruments – 750-mA Single-Chip Li-Ion and Li-Pol Charge Management IC With Thermal Regulation

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SLUS784E – DECEMBER 2007 – REVISED DECEMBER 2015
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7.6 Timing Requirements
over recommended operating range, T_J = 0 –125°C range, See the Application and Implementation section, typical values at
T_J = 25°C (unless otherwise noted), R_TMR = 49.9 KΩ
PARAMETER
TEST CONDITIONS
MIN TYP MAX UNIT
POWER DOWN THRESHOLD – UNDERVOLTAGE LOCKOUT
t_DGL(PG)
Deglitch time on power good
INPUT POWER DETECTION⁽¹⁾
V_(IN) = 0 V → 5 V in 1 μs to
PG:HI → LO
2
ms
t_DGL(NOIN)
Delay time, input power not detected
status ⁽²⁾
PG: LO →HI after t_DGL(NOIN)
10 μs
t_DLY(CHGOFF) Charger off delay
INPUT OVERVOLTAGE PROTECTION
Charger turned off after t_DLY(CHGOFF), Measured
from PG: LO → HI; Timer reset after t_DLY(CHGOFF)
25
ms
t_DGL(OVDET) Input overvoltage detection delay
CE = HI or LO, Measured from V_(IN) > V_(OVP) to
PG: LO → HI; VIN increasing
100 μs
t_DGL(OVNDET) Input overvoltage not detected delay⁽²⁾
VOLTAGE AND CURRENT REGULATION TIMING⁽³⁾
CE = HI or LO, Measured from V_(IN) < V_(OVP)
to PG: HI → LO; V(IN) decreasing
100 μs
t_PWRUP(CHG)
Input power detection to full charge
current time delay
Measured from PG:HI → LO to I_(OUT) > 100 mA,
CE = LO, I_O(OUT) = 750 mA, V(BAT) = 3.5 V
25
ms
t_PWRUP(EN)
Charge enable to full charge current
delay
Measured from CE:HI → LO to I_(OUT) >100 mA,
I_O(OUT) = 750 mA, V_(BAT)= 3.5 V, V_(IN) = 4.5 V,
Input power detected
25
ms
t_PWRUP(LDO)
Input power detection to voltage
regulation delay, LDO mode set, no
battery or load connected
CHARGE TERMINATION DETECTION⁽⁴⁾
Measured from PG:HI → LO to V_(OUT) > 90% of
charge voltage regulation;
V_(TMR) = OPEN, LDO mode set, no battery and
no load at OUT pin, CE = LO
25
ms
t_DGL(TERM)
Deglitch time, termination detected
BATTERY RECHARGE THRESHOLD
V_(ISET) decreasing
50
ms
t_DGL(RCH)
TIMERS ⁽⁵⁾
Deglitch time, recharge detection
V_(BAT) decreasing
350
ms
t_(CHG)
K_(CHG)
t_(PCHG)
Charge safety timer range
Charge safety timer constant
Pre-charge safety timer range
t_(CHG) = K_(CHG) × R_TMR ; thermal loop not active
V_(BAT) > V_(LOWV)
t_(PCHG) = K_(PCHG) × t_(CHG) ; Thermal regulation
loop not active
3
0.08
1080
10 hours
0.1 0.12 hr/kΩ
3600 s
K_(PCHG)
Pre-charge safety timer constant
BATTERY DETECTION THRESHOLDS
V_(BAT) < V_(LOWV)
0.08 0.1 0.12
t_(DETECT)
Battery detection time
2 V < V_(BAT) < V_O(REG), Thermal regulation loop
not active; R_TMR = 50 kΩ, I_DET(down) or I_{DET (UP)}
125
ms
(1) CE = HI or LOW, V_(IN) > 3.5 V
(2) Specified by design, not production tested.
(3) V_(IN) > V_(OUT) + V_(DO-MAX), charger enabled, no fault conditions detected, R_TMR = 50 K or V(TMR) = OPEN; thermal regulation loop not
active.
(4) V_O(REG) = 4.2 V, charger enabled, no fault conditions detected, thermal regulation loop not active, R_TMR = 50 K or TMR pin open.
(5) CE = LO, charger enabled, no fault conditions detected, V(TMR) < 3 V, timers enabled.
7.7 Dissipation Ratings⁽¹⁾
PACKAGE
10-pin DRC
θ_JC (°C/W)
3.21
θ_JA (°C/W)
46.87
(1) This data is based on using the JEDEC High-K board and the exposed die pad is connected to a copper pad on the board. This is
connected to the ground plane by a 2×3 via matrix.
8
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