5962-9865201QFA Datasheet, PDF (8/16 Pages) Texas Instruments – DS90LV032AQML 3V LVDS Quad CMOS Differential Line Receiver

DS90LV032AQML
SNLS205A – NOVEMBER 2011 – REVISED APRIL 2013
TYPICAL APPLICATION
Balanced System
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Figure 12. Point-to-Point Application
APPLICATION INFORMATION
General application guidelines and hints for LVDS drivers and receivers may be found in the LVDS Owner's
Manual at http://www.ti.com/ww/en/analog/interface/lvds.shtml
LVDS drivers and receivers are intended to be primarily used in an uncomplicated point-to-point configuration as
is shown in Figure 12. This configuration provides a clean signaling environment for the fast edge rates of the
drivers . The receiver is connected to the driver through a balanced media which may be a standard twisted pair
cable, a parallel pair cable, or simply PCB traces. Typically the characteristic impedance of the media is in the
range of 100Ω. A termination resistor of 100Ω should be selected to match the media, and is located as close to
the receiver input pins as possible. The termination resistor converts the driver output (current mode) into a
voltage that is detected by the receiver. Other configurations are possible such as a multi-receiver configuration,
but the effects of a mid-stream connector(s), cable stub(s), and other impedance discontinuities as well as
ground shifting, noise margin limits, and total termination loading must be taken into account.
The DS90LV032A differential line receiver is capable of detecting signals as low as 100 mV, over a ±1V
common-mode range centered around +1.2V. This is related to the driver offset voltage which is typically +1.2V.
The driven signal is centered around this voltage and may shift ±1V around this center point. The ±1V shifting
may be the result of a ground potential difference between the driver's ground reference and the receiver's
ground reference, the common-mode effects of coupled noise, or a combination of the two. Both receiver input
pins have a recommended operating input voltage range of 0V to +2.4V (measured from each pin to ground),
exceeding these limits may turn on the ESD protection circuitry which will clamp the bus voltages.
POWER DECOUPLING RECOMMENDATIONS
Bypass capacitors must be used on power pins. High frequency ceramic (surface mount is recommended) 0.1μF
in parallel with 0.01μF, in parallel with 0.001μF at the power supply pin as well as scattered capacitors over the
printed circuit board. Multiple vias should be used to connect the decoupling capacitors to the power planes A
10μF (35V) or greater solid tantalum capacitor should be connected at the power entry point on the printed circuit
board.
PC BOARD CONSIDERATIONS
Use at least 4 PCB layers (top to bottom); LVDS signals, ground, power, TTL signals.
Isolate TTL signals from LVDS signals, otherwise the TTL may couple onto the LVDS lines. It is best to put TTL
and LVDS signals on different layers which are isolated by a power/ground plane(s).
Keep drivers and receivers as close to the (LVDS port side) connectors as possible.
DIFFERENTIAL TRACES
Use controlled impedance traces which match the differential impedance of your transmission medium (ie. cable)
and termination resistor. Run the differential pair trace lines as close together as possible as soon as they leave
the IC (stubs should be < 10mm long). This will help eliminate reflections and ensure noise is coupled as
common-mode. Lab experiments show that differential signals which are 1mm apart radiate far less noise than
traces 3mm apart since magnetic field cancellation is much better with the closer traces. Plus, noise induced on
the differential lines is much more likely to appear as common-mode which is rejected by the receiver.
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