5962-9865201QFA Datasheet, PDF (5/16 Pages) Texas Instruments – DS90LV032AQML 3V LVDS Quad CMOS Differential Line Receiver

DS90LV032AQML
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DS90LV032A Electrical Characteristics AC Parameters
The following conditions apply, unless otherwise specified.
AC: V_CC = 3.15 / 3.3 / 3.45V, C_L = 20pF
Symbol
Parameter
Conditions
t_PHLD
t_PLHD
t_SkD
Differential Propagation Delay
High to Low
Differential Propagation Delay
Low to High
Differential Skew |t_PHLD - t_PLHD|
V_ID = 200mV,
Input pulse = 1.1V to 1.3V,
V_I = 1.2V (0V differential) to
V_O = 1/2 V_CC
V_ID = 200mV,
Input pulse = 1.1V to 1.3V,
V_I = 1.2V (0V differential) to
V_O = 1/2 V_CC
C_L = 20pF, V_ID = 200mV
t_Sk1
Channel to Channel Skew
C_L = 20pF, V_ID = 200mV
t_Sk2
Chip to Chip Skew
C_L = 20pF, V_ID = 200mV
t_PLZ
Disable Time Low to Z
Input pulse = 0V to 3.0V,
V_I = 1.5V, V_O = V_OL+0.5V,
R_L= 1kΩ.
t_PHZ
Disable Time High to Z
Input pulse = 0V to 3.0V,
V_I = 1.5V, V_O = V_OH-0.5V,
R_L = 1kΩ.
t_PZH
Enable Time Z to High
Input pulse = 0V to 3.0V,
V_I = 1.5V, V_O = 50%,
R_L = 1kΩ.
t_PZL
Enable Time Z to Low
Input pulse = 0V to 3.0V,
V_I = 1.5V, V_O = 50%,
R_L = 1kΩ.
SNLS205A – NOVEMBER 2011 – REVISED APRIL 2013
Notes
Figure 3
and
Figure 4
Min Max
0.5 3.5
Figure 3 0.5 3.5
and
Figure 4
Figure 3
and
Figure 4
(1)
(2)
1.5
1.75
3.0
Figure 5
12
and
Figure 6
Figure 5
12
and
Figure 6
Figure 5
20
and
Figure 6
Figure 5
20
and
Figure 6
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
Sub-
groups
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
(1) Channel-to-Channel Skew, is defined as the difference between the propagation delay of one channel and that of the others on the
same chip with any event on the inputs.
(2) Chip to chip Skew is defined as the difference between the minimum and maximum specified differential propagation delays.
PARAMETER MEASUREMENT INFORMATION
Figure 3. Receiver Propagation Delay and Transition Time Test Circuit
Figure 4. Receiver Propagation Delay and Transition Time Waveforms
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