TM4C1294KCPDT Datasheet, PDF (790/1890 Pages) Texas Instruments – Tiva Microcontroller

General-Purpose Input/Outputs (GPIOs)
Register 26: GPIO 12-mA Drive Select (GPIODR12R), offset 0x53C
The GPIODR12R register is the 12-mA drive control register. Each GPIO signal in the port can be
individually configured without affecting the other pads.
Note: This register has no effect on port pins PL6 and PL7 or PM[7:4].
GPIO 12-mA Drive Select (GPIODR12R)
GPIO Port A (AHB) base: 0x4005.8000
GPIO Port B (AHB) base: 0x4005.9000
GPIO Port C (AHB) base: 0x4005.A000
GPIO Port D (AHB) base: 0x4005.B000
GPIO Port E (AHB) base: 0x4005.C000
GPIO Port F (AHB) base: 0x4005.D000
GPIO Port G (AHB) base: 0x4005.E000
GPIO Port H (AHB) base: 0x4005.F000
GPIO Port J (AHB) base: 0x4006.0000
GPIO Port K (AHB) base: 0x4006.1000
GPIO Port L (AHB) base: 0x4006.2000
GPIO Port M (AHB) base: 0x4006.3000
GPIO Port N (AHB) base: 0x4006.4000
GPIO Port P (AHB) base: 0x4006.5000
GPIO Port Q (AHB) base: 0x4006.6000
Offset 0x53C
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
DRV12
Type RO
RO
RO
RO
RO
RO
RO
RO
RW
RW
RW
RW
RW
RW
RW
RW
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:8
7:0
Name
reserved
DRV12
Type
RO
RW
Reset Description
0x0000.00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00 Output Pad 12-mA Drive Enable
Value Description
0 The drive for the corresponding GPIO pin is controlled by the
GPIODR2R, GPIODR4R, and/or the GPIODR8R register.
1 The corresponding GPIO pin has 12-mA drive. This encoding
is only valid if the GPIOPP EDE bit is set and the appropriate
GPIOPC EDM bit field is programmed to 0x3.
Note: Please refer to Table 10-3 on page 751 for information on how
to configure the drive strength.
Changes in the GPIODR2R, the GPIODR4R register and/or the
GPIODR8R registers to configure 12 mA are effective on the next clock
cycle.
790
June 18, 2014
Texas Instruments-Production Data