TM4C1294KCPDT Datasheet, PDF (28/1890 Pages) Texas Instruments – Tiva Microcontroller

Table of Contents
Register 118: Analog-to-Digital Converter Sleep Mode Clock Gating Control (SCGCADC), offset
0x738 ........................................................................................................................... 420
Register 119: Analog Comparator Sleep Mode Clock Gating Control (SCGCACMP), offset 0x73C .......... 421
Register 120: Pulse Width Modulator Sleep Mode Clock Gating Control (SCGCPWM), offset 0x740 ........ 422
Register 121: Quadrature Encoder Interface Sleep Mode Clock Gating Control (SCGCQEI), offset
0x744 ........................................................................................................................... 423
Register 122: EEPROM Sleep Mode Clock Gating Control (SCGCEEPROM), offset 0x758 ..................... 424
Register 123: CRC Module Sleep Mode Clock Gating Control (SCGCCCM), offset 0x774 ....................... 425
Register 124: Ethernet MAC Sleep Mode Clock Gating Control (SCGCEMAC), offset 0x79C .................. 426
Register 125: Watchdog Timer Deep-Sleep Mode Clock Gating Control (DCGCWD), offset 0x800 .......... 427
Register 126: 16/32-Bit General-Purpose Timer Deep-Sleep Mode Clock Gating Control (DCGCTIMER),
offset 0x804 .................................................................................................................. 428
Register 127: General-Purpose Input/Output Deep-Sleep Mode Clock Gating Control (DCGCGPIO), offset
0x808 ........................................................................................................................... 430
Register 128: Micro Direct Memory Access Deep-Sleep Mode Clock Gating Control (DCGCDMA), offset
0x80C ........................................................................................................................... 433
Register 129: EPI Deep-Sleep Mode Clock Gating Control (DCGCEPI), offset 0x810 ............................. 434
Register 130: Hibernation Deep-Sleep Mode Clock Gating Control (DCGCHIB), offset 0x814 .................. 435
Register 131: Universal Asynchronous Receiver/Transmitter Deep-Sleep Mode Clock Gating Control
(DCGCUART), offset 0x818 ............................................................................................ 436
Register 132: Synchronous Serial Interface Deep-Sleep Mode Clock Gating Control (DCGCSSI), offset
0x81C ........................................................................................................................... 438
Register 133: Inter-Integrated Circuit Deep-Sleep Mode Clock Gating Control (DCGCI2C), offset
0x820 ........................................................................................................................... 439
Register 134: Universal Serial Bus Deep-Sleep Mode Clock Gating Control (DCGCUSB), offset
0x828 ........................................................................................................................... 441
Register 135: Ethernet PHY Deep-Sleep Mode Clock Gating Control (DCGCEPHY), offset 0x830 ........... 442
Register 136: Controller Area Network Deep-Sleep Mode Clock Gating Control (DCGCCAN), offset
0x834 ........................................................................................................................... 443
Register 137: Analog-to-Digital Converter Deep-Sleep Mode Clock Gating Control (DCGCADC), offset
0x838 ........................................................................................................................... 444
Register 138: Analog Comparator Deep-Sleep Mode Clock Gating Control (DCGCACMP), offset
0x83C ........................................................................................................................... 445
Register 139: Pulse Width Modulator Deep-Sleep Mode Clock Gating Control (DCGCPWM), offset
0x840 ........................................................................................................................... 446
Register 140: Quadrature Encoder Interface Deep-Sleep Mode Clock Gating Control (DCGCQEI), offset
0x844 ........................................................................................................................... 447
Register 141: EEPROM Deep-Sleep Mode Clock Gating Control (DCGCEEPROM), offset 0x858 ........... 448
Register 142: CRC Module Deep-Sleep Mode Clock Gating Control (DCGCCCM), offset 0x874 .............. 449
Register 143: Ethernet MAC Deep-Sleep Mode Clock Gating Control (DCGCEMAC), offset 0x89C ......... 450
Register 144: Watchdog Timer Power Control (PCWD), offset 0x900 ..................................................... 451
Register 145: 16/32-Bit General-Purpose Timer Power Control (PCTIMER), offset 0x904 ....................... 453
Register 146: General-Purpose Input/Output Power Control (PCGPIO), offset 0x908 .............................. 456
Register 147: Micro Direct Memory Access Power Control (PCDMA), offset 0x90C ................................ 461
Register 148: External Peripheral Interface Power Control (PCEPI), offset 0x910 ................................... 463
Register 149: Hibernation Power Control (PCHIB), offset 0x914 ............................................................ 465
Register 150: Universal Asynchronous Receiver/Transmitter Power Control (PCUART), offset 0x918 ...... 467
Register 151: Synchronous Serial Interface Power Control (PCSSI), offset 0x91C .................................. 470
Register 152: Inter-Integrated Circuit Power Control (PCI2C), offset 0x920 ............................................ 472
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June 18, 2014
Texas Instruments-Production Data