TM4C1294KCPDT Datasheet, PDF (1568/1890 Pages) Texas Instruments – Tiva Microcontroller

Ethernet Controller
Bit/Field
6
5
4:3
2
Name
FUF
DGF
RTC
OSF
Type
RW
RW
RW
RW
Reset
0x0
Description
Forward Undersized Good Frames
Value Description
0 The Receive FIFO drops all frames of less than 64 bytes, unless
a frame is already transferred because of the lower value of
Receive Threshold (RTC) bit field (for example, RTC = 0x1).
1 The Receive FIFO forwards undersized frames (frames with no
Error and length less than 64 bytes) including pad-bytes and
CRC.
0x0
Drop Giant Frame Enable
Value Description
0 The MAC does not drop the giant frames in the RX FIFO.
1 The MAC drops received frames larger than the computed giant
frame limit in the RX FIFO.
0x0
Receive Threshold Control
These two bits control the threshold level of the RX FIFO. Transfer
(request) to DMA starts when the frame size within the RX FIFO is larger
than the threshold. In addition, full frames with length less than the
threshold are transferred automatically.
These bits are valid only when the RSF bit (bit 25) of the
EMACDMAOPMODE is zero, and are ignored when the RSF bit is set
to 1.
Value Description
0x0 64 bytes
0x1 32 bytes
0x2 96 bytes
0x3 128 bytes
0x0
Operate on Second Frame
Value Description
0 DMA processes frames normally.
1 DMA processes second frame of the Transmit data even before
the status for the first frame is obtained.
1568
Texas Instruments-Production Data
June 18, 2014