TMS320TCI6487ZUN Datasheet, PDF (79/219 Pages) Texas Instruments – TMS320TCI6487/8 Communications Infrastructure Digital Signal Processor

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8 Peripheral Information and Electrical Specifications
TMS320TCI6487
TMS320TCI6488
SPRS358L – APRIL 2007 – REVISED APRIL 2011
8.1 Parameter Information
DDR2 Output Test Load
Transmission Line
Z0 = 50 W
4 pf
Data Sheet Timing
Reference Point
Device Pin^(A)
Output Test Load Excluding DDR2
Transmission Line
Z0 = 50 W
5 pf
Device
Device
A. The data sheet provides timing at the device pin. For output analysis, the transmission line and associated parasitics
(vias, multiple nodes, etc.) must also be taken into account. The transmission line delay varies depending on the trace
length. An approximate range for output delays can vary from 176 ps to 2 ns depending on the end product design.
For recommended transmission line lengths, see the appropriate application notes, user's guides, and design guides.
A transmission line delay of 2 ns was used for all output measurements, except the DDR2 which was evaluated using
a 528-ps delay.
B. This figure represents all outputs, except differential or I2C.
Figure 8-1. Test Load Circuit for AC Timing Measurements
The load capacitance value stated is for characterization and measurement of AC timing signals. This load
capacitance value does not indicate the maximum load the device is capable of driving.
8.1.1 1.8 V Signal Transition Levels
All input and output timing parameters are referenced to 0.9 V for both "0" and "1" logic levels.
Vref = 0.9 V
Figure 8-2. Input and Output Voltage Reference Levels for AC Timing Measurements
All rise and fall transition timing parameters are reference to V_IL MAX and V_IH MIN for input clocks.
V_ref = V_IHMIN (or V_OHMIN)
V_ref = V_ILMAX (or V_OLMAX)
Figure 8-3. Rise and Fall Transition Time Voltage Reference Levels
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Peripheral Information and Electrical Specifications
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