TMS320TCI6487ZUN Datasheet, PDF (148/219 Pages) Texas Instruments – TMS320TCI6487/8 Communications Infrastructure Digital Signal Processor

TMS320TCI6487
TMS320TCI6488
SPRS358L – APRIL 2007 – REVISED APRIL 2011
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Table 8-45. Switching Characteristics Over Recommended Operating Conditions for McBSP^{(1) (2)}
(see Figure 8-28)
NO.
MIN
MAX UNIT
1 t_{d(CKSH-CKRXH)} Delay time, CLKS high to CLKR/X high for internal CLKR/X
generated from CLKS input.⁽³⁾
2
t_c(CKRX)
3
t_w(CKRX)
Cycle time, CLKR/X
Pulse duration, CLKR/X high or
CLKR/X low
CLKR/X int
CLKR/X int
1.4
10P ⁽⁴⁾
C - 1 ⁽⁵⁾
10 ns
ns
C + 1⁽⁵⁾ ns
4
t_d(CKRH-FRV)
Delay time, CLKR high to internal CLKR int
FSR valid
-2.1
3 ns
9
t_d(CKXH-FXV)
Delay time, CLKX high to internal CLKX int
FSX valid
CLKX ext
-1.7
3 ns
1.7
9
12 t_{dis(CKXH-DXHZ)} Disable time, DX high impedance CLKX int
following last data bit from CLKX
high
CLKX ext
CLKX int
13
t_d(CKXH-DXV)
Delay time, CLKX high to DX valid CLKX ext (DXENA = 0)
CLKX ext (DXENA = 1)
14
t_d(FXH-DXV)
Delay time, FSX high to DX valid FSX int
ONLY applies when in data delay
0 (XDATDLY = 00b)mode
FSX ext
-3.9
2.1
-3.9 +D1⁽⁶⁾
2.1 ⁽⁶⁾
2.1 + D1⁽⁶⁾
-2.3 + D1⁽⁷⁾
1.9 + D1⁽⁷⁾
4 ns
9
4 + D2⁽⁶⁾ ns
9 ⁽⁶⁾
9 + D2⁽⁶⁾
5.6 + D2⁽⁷⁾ ns
9 + D2⁽⁷⁾
(1) CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also
inverted.
(2) Minimum delay times also represent minimum output hold times.
(3) The CLKS signal is shared by both McBSP0 and McBSP1 on this device.
(4) P = 1/CPU clock frequency, in ns. For example, when running parts at 1000 MHz, use P = 1 ns.
(5) C = H or L S = sample rate generator input clock = 6P if CLKSM = 1 (P = 1/CPU clock frequency)
S = sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
H = (CLKGDV + 1)/2 * S if CLKGDV is odd L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
L = (CLKGDV + 1)/2 * S if CLKGDV is odd CLKGDV should be set appropriately to ensure the McBSP bit rate does not exceed the
maximum limit (see (4) above).
(6) Extra delay from CLKX high to DX valid applies only to the first data bit of a device, if and only if DXENA = 1 in SPCR.
if DXENA = 0, then D1 = D2 = 0
if DXENA = 1, then D1 = 6P, D2 = 12P
(7) Extra delay from FSX high to DX valid applies only to the first data bit of a device, if and only if DXENA = 1 in SPCR.
if DXENA = 0, then D1 = D2 = 0
if DXENA = 1, then D1 = 6P, D2 = 12P
148 Peripheral Information and Electrical Specifications
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