TMS320TCI6487ZUN Datasheet, PDF (44/219 Pages) Texas Instruments – TMS320TCI6487/8 Communications Infrastructure Digital Signal Processor

TMS320TCI6487
TMS320TCI6488
SPRS358L – APRIL 2007 – REVISED APRIL 2011
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an overview of the 64-bit timer in the TMS320C6472/TMS320TCI648x DSP.
SPRU894
TMS320C6472/TMS320TCI648x DSP DDR2 Memory Controller User's Guide. This
document describes the DDR2 memory controller in the TMS320C6472/TMS320TCI648x
digital signal processors (DSPs).
SPRUE09
TMS320TCI648x DSP Viterbi-Decoder Coprocessor 2 (VCP2) Reference Guide. This
document describes the operation and programming of the VCP2 in the TMS320TCI648x
digital signal processors (DSPs).
SPRUE10
TMS320TCI648x DSP Turbo-Decoder Coprocessor 2 (TCP2) Reference Guide. This
document describes the operation and programming of the TCP2 in the TMS320TCI648x
digital signal processors (DSPs).
SPRUE11
TMS320C6472/TMS320TCI648x DSP Inter-Integrated Circuit (I2C) Module User's Guide.
This document describes the inter-integrated circuit (I2C) module in the
TMS320C6472/TMS320TCI648x digital signal processors (DSPs).
SPRUE13 TMS320C6472/TMS320TCI648x Serial RapidIO (SRIO) User's Guide. This document
describes the Serial RapidIO (SRIO) on the TMS320C6472/TMS320TCI648x devices.
SPRUEE9 TMS320TCI6487/8 DSP Enhanced DMA (EDMA3) Controller User's Guide. This
document describes the Enhanced DMA (EDMA3) Controller on the TMS320TCI6487/8
digital signal processors (DSPs).
SPRUEF0
TMS320TCI6487/8 DSP Ethernet Media Access Controller (EMAC)/ Management Data
Input/Output (MDIO) User's Guide. This document provides a functional description of the
Ethernet Media Access Controller (EMAC) and Physical layer (PHY) device Management
Data Input/Output (MDIO) module integrated with the TMS320TCI6487/8 digital signal
processors (DSPs).
SPRUEF1
TMS320TCI6487/8 DSP Software-Programmable Phase-Locked Loop (PLL) Controller
User's Guide. This document describes the operation of the software-programmable
phase-locked loop (PLL) controller in the TMS320TCI6487/8 digital signal processors
(DSPs).
SPRUEF3 TMS320TCI6487/8 Power/Sleep Controller (PSC) User's Guide. This document describes
the Power/Sleep Controller (PSC) for the TMS320TCI6487/8 digital signal processors
(DSPs).
SPRUEF4 TMS320TCI6487/8 Antenna Interface User's Guide. This document describes the Antenna
Interface module on the TMS320TCI6487/8 digital signal processors (DSPs).
SPRUEF5 TMS320TCI6487/8 Frame Synchronization User's Guide. This document describes the
reference guide for Frame Synchronization module on the TMS320TCI6487/8 digital signal
processors (DSPs).
SPRUEF6 TMS320TCI6487/8 Semaphore User's Guide. This document describes the usage of the
semaphore and some of the CSL calls used to configure/use the Semaphore module on the
TMS320TCI6487/8 digital signal processors (DSPs).
SPRUEJ0
TMS320TCI6488 Receive Accelerator (RAC) User's Guide. This manual describes the
receive accelerator co-processor (RAC) on the TMS320TCI6488 digital signal processor
(DSP).
SPRUG70 TMS320TCI6487/8 DSP Chip Interrupt Controller (CIC) User's Guide. This document
describes the system event routing using the chip interrupt controller (CIC) for the
TMS320TCI6487/8 digital signal processors (DSPs).
SPRAAG5 TMS320TCI6488 Hardware Design Guide. This document describes hardware system
design considerations for the TMS320TCI6488.
SPRAAG6 TMS320TCI6484/6487/6488 DDR2 Implementation Guidelines. This document provides
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Device Overview
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