TMS320VC5501_17 Datasheet, PDF (76/197 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

Functional Overview
3.9.6 Reset Sequence
When RESET is low, the clock generator is in bypass mode with the input clock set to CLKIN or X2/CLKIN,
dependent upon the state of GPIO4. After the RESET pin transitions from low to high, the following events
will occur in the order listed below.
• GPIO6 is sampled on the rising edge of the reset signal. The state of GPIO6 determines the function of
the multiplexed pins of the 5501. (See Section 3.3, Configurable External Ports and Signals, for more
information on pin multiplexing.) The state of GPIO6 during the rising edge of reset determines the value
of the Parallel/Host Port Mux Mode bit of the External Bus Control Register (XBSR).
• GPIO4 is sampled on the rising edge of the reset signal to set the state of the CLKMD0 bit of the Clock
Mode Control Register (CLKMD), which in turns, determines the clock source for the DSP. The CLKMD0
bit selects either the internal oscillator output (OSCOUT) or the X2/CLKIN pin as the input clock source
for the DSP. If GPIO4 is low at reset, the CLKMD0 bit will be set to 0 and the internal oscillator and the
external crystal generate the input clock for the DSP. If GPIO4 is high, the CLKMD0 bit will be set to 1 and
the input clock will be taken directly from the X2/CLKIN pin.
• After the reset signal transitions from low to high, the DSP will not be taken out of reset immediately.
Instead, an internal counter will count 41032 clock cycles to allow the internal oscillator to stabilize (only
if GPIO4 was low). The internal counter will also add 70 reference clock cycles to allow the reset signal
to propagate through different parts of the device.
• After all internal delay cycles have expired, the IACK pin will go low for two CPU clock cycles to indicate
this internal reset signal has been deasserted. The BOOTM[2:0] pins will be sampled and their values will
be stored in the Boot Mode Register (BOOTM_MODE). The value in the BOOTM_MODE register will be
used by the bootloader to determine the boot mode of the DSP.
• Program flow will commence after all internal delay cycles have expired.
The 5501 has internal circuitry that will count down 70 reference clock cycles to allow reset signals to
propagate correctly to all parts of the device after reset (RESET pin goes high). Furthermore, the 5501 also
has internal circuitry that will count down 41,032 reference clock cycles to allow the oscillator input to become
stable after waking up from power-down state or reset. If a reset is asserted, program flow will start after all
stabilization periods have expired; this includes the oscillator stabilization period only if GPIO4 is low at reset.
If the oscillator is coming out of power-down mode, program flow will start immediately after the oscillator
stabilization period has completed. Table 3−23 summarizes the number of reference clock cycles needed
before program flow begins.
Table 3−23. Number of Reference Clock Cycles Needed Until Program Flow Begins
CONDITION
REFERENCE CLOCK
CYCLES
After Reset
Oscillator Not Used (GPIO4 = 1)
Oscillator Used (GPIO4 = 0)
70
41,102
After Oscillator Power-Down
41,032
All output (O/Z) and input/output (I/O/Z) pins (except for CLKOUT, ECLKOUT2, and XF) will go into
high-impedance mode during reset and will come out of high-impedance mode when the stabilization periods
have expired. All output (O/Z) and input/output (I/O/Z) pins will retain their value when the device enters a
power-down mode such as IDLE3 mode.
76 SPRS206K
December 2002 − Revised November 2008