TMS320VC5501_17 Datasheet, PDF (51/197 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

Functional Overview
3.4.1 Timer Interrupts
As stated earlier, each timer has one input, one output, and one interrupt signal: TIN, TOUT, and TINT,
respectively. The interrupt signals of Timer 0 and Timer 1 are directly connected to the interrupt logic of the
DSP (see Figure 3−6). The interrupts for Timer 0 and Timer 1 are maskable and can be enabled or disabled
through the TINT0 and TINT1 bits of the interrupt enable registers (IER0 and IER1); setting TINT0 of IER0
to ‘1’ enables the interrupt for Timer 0 and setting TINT1 of IER1 enables the interrupt for Timer 1.
TMS320VC5501 DSP
RESET
INT3
Interrupt Logic
NMI
TINT1 TINT0
10 Others
01
11
10
Timer0
TINT
Timer1
TINT
Watchdog
Timer
TINT
IWCON
RESET
INT3
Figure 3−6. Timer Interrupts
NMI/WDTOUT
The interrupt signal for the Watchdog Timer can be internally connected to the RESET, INT3, or NMI signals
by setting the IWCON bit of the Timer Signal Selection Register (TSSR) appropriately (see Figure 3−6). The
DSP will be reset once the Watchdog Timer generates an interrupt if the timer interrupt is connected to RESET
(IWCON = ‘01’). A non-maskable interrupt will be generated if the timer interrupt is connected to NMI (IWCON
= ‘10’). An external interrupt will be generated when the timer interrupt signal is connected to INT3 (IWCON
= ‘11’), but only if the INT3 bit of IER0 is set to ‘1’.
Refer to Section 3.16, Interrupts, for more information on using interrupts.
December 2002 − Revised November 2008
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