TMS320VC5501_17 Datasheet, PDF (72/197 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

Functional Overview
3.9.5.7 Oscillator Divider1 Register (OSCDIV1) for CLKOUT3
This register controls the value of the divider OD1 for CLKOUT3. It does not go through the PLL path.
15
14
8
OD1EN
R/W, 0
Reserved
R, 0000000
7
5
4
0
Reserved
OSCDIV1
R, 000
LEGEND: R = Read, W = Write, n = value at reset
R/W, 00000
Figure 3−21. Oscillator Divider1 Register Layout (0x1C92)
BIT NAME
OD1EN
Reserved
OSCDIV1
Table 3−18. Oscillator Divider1 Register Bit Field Description
BIT NO.
ACCESS
RESET VALUE
DESCRIPTION
15
R/W
0
Oscillator divider OD1 enable
OD1EN = 0:
OD1EN = 1:
Oscillator divider 1 disabled
Oscillator divider 1 enabled
14:5
R
0000000000 Reserved. Reads return 0. Writes have no effect.
4:0
R/W
00000
Divider OD1 ratio (CLKOUT3 divider)
OSCDIV1 = 00000:
OSCDIV1 = 00001:
OSCDIV1 = 00010:
OSCDIV1 = 00011:
OSCDIV1 = 00100:
OSCDIV1 = 00101:
OSCDIV1 = 00110:
OSCDIV1 = 00111:
OSCDIV1 = 01000:
OSCDIV1 = 01001:
OSCDIV1 = 01010:
OSCDIV1 = 01011:
OSCDIV1 = 01100:
OSCDIV1 = 01101:
OSCDIV1 = 01110:
OSCDIV1 = 01111:
OSCDIV1 = 10000:
OSCDIV1 = 10001:
OSCDIV1 = 10010:
OSCDIV1 = 10011:
OSCDIV1 = 10100:
OSCDIV1 = 10101:
OSCDIV1 = 10110:
OSCDIV1 = 10111:
OSCDIV1 = 11000:
OSCDIV1 = 11001:
OSCDIV1 = 11010:
OSCDIV1 = 11011:
OSCDIV1 = 11100:
OSCDIV1 = 11101:
OSCDIV1 = 11110:
OSCDIV1 = 11111:
Divide by 1
Divide by 2
Divide by 3
Divide by 4
Divide by 5
Divide by 6
Divide by 7
Divide by 8
Divide by 9
Divide by 10
Divide by 11
Divide by 12
Divide by 13
Divide by 14
Divide by 15
Divide by 16
Divide by 17
Divide by 18
Divide by 19
Divide by 20
Divide by 21
Divide by 22
Divide by 23
Divide by 24
Divide by 25
Divide by 26
Divide by 27
Divide by 28
Divide by 29
Divide by 30
Divide by 31
Divide by 32
72 SPRS206K
December 2002 − Revised November 2008