TMS320VC5501_17 Datasheet, PDF (100/197 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

Functional Overview
3.11.2.6 Parallel GPIO Data Register 1 (PGPIODAT1)
15
14
13
12
11
10
9
8
IO31DAT
R/W, pin
7
IO30DAT
R/W, pin
6
IO29DAT
R/W, pin
5
IO28DAT
R/W, pin
4
IO27DAT
R/W, pin
3
IO26DAT
R/W, pin
2
IO25DAT
R/W, pin
1
IO24DAT
R/W, pin
0
IO23DAT
IO22DAT
IO21DAT
IO20DAT
IO19DAT
IO18DAT
IO17DAT
IO16DAT
R/W, pin
R/W, pin
R/W, pin
R/W, pin
R/W, pin
R/W, pin
R/W, pin
R/W, pin
LEGEND: R = Read, W = Write, n = value at reset, pin = the reset value depends on the signal level on the corresponding I/O pin.
Figure 3−39. Parallel GPIO Data Register 1 Layout (0x4405)
BIT NAME
IOxDAT
Table 3−41. Parallel GPIO Data Register 1 Bit Field Description^†
BIT NO. ACCESS
RESET VALUE
DESCRIPTION
15−0
R/W
Depends on the signal level on Data bits that are used to either control the level of the
the corresponding I/O pin
corresponding I/O pins configured as output pins or to
monitor the level of the corresponding I/O pins configured as
input pins. The function of the data register bits is
determined by the setting of the direction register bits. See
Table 3−35, TMS320VC5501 PGPIO Cross-Reference to
determine which device pins correspond to the PGPIO pins.
If IOxEN = 0 and IOxDIR = 0, then IOxDAT is used to read
the value of the PGPIOx pin:
IOxDAT = 0: PGPIOx pin is read as a low
IOxDAT = 1: PGPIOx pin is read as a high
If IOxEN = 1 and IOxDIR = 1, then IOxDAT is used to set
the value of the PGPIOx pin:
IOxDAT = 0: Set PGPIOx pin to low
IOxDAT = 1: Set PGPIOx pin to high
† _{x = value from 16 to 31}
Note that other combinations of IOxEN and IOxDIR are not
supported—i.e., IOxEN and IOxDIR must always be set to
the same value.
100 SPRS206K
December 2002 − Revised November 2008