TM4C123GE6PZ Datasheet, PDF (754/1445 Pages) Texas Instruments – Tiva™ TM4C123GE6PZ Microcontroller

General-Purpose Timers
Register 5: GPTM Synchronize (GPTMSYNC), offset 0x010
Note: This register is only implemented on GPTM Module 0 only.
This register allows software to synchronize a number of timers.
GPTM Synchronize (GPTMSYNC)
16/32-bit Timer 0 base: 0x4003.0000
16/32-bit Timer 1 base: 0x4003.1000
16/32-bit Timer 2 base: 0x4003.2000
16/32-bit Timer 3 base: 0x4003.3000
16/32-bit Timer 4 base: 0x4003.4000
16/32-bit Timer 5 base: 0x4003.5000
32/64-bit Wide Timer 0 base: 0x4003.6000
32/64-bit Wide Timer 1 base: 0x4003.7000
32/64-bit Wide Timer 2 base: 0x4004.C000
32/64-bit Wide Timer 3 base: 0x4004.D000
32/64-bit Wide Timer 4 base: 0x4004.E000
32/64-bit Wide Timer 5 base: 0x4004.F000
Offset 0x010
Type RW, reset 0x0000.0000
31
30
29
28
27
26
reserved
Type RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
Type
Reset
15
14
SYNCWT1
RW
RW
0
0
13
12
SYNCWT0
RW
RW
0
0
11
10
SYNCT5
RW
RW
0
0
25
24
RO
RO
0
0
9
8
SYNCT4
RW
RW
0
0
23
22
SYNCWT5
RW
RW
0
0
7
6
SYNCT3
RW
RW
0
0
21
20
SYNCWT4
RW
RW
0
0
5
4
SYNCT2
RW
RW
0
0
19
18
SYNCWT3
RW
RW
0
0
3
2
SYNCT1
RW
RW
0
0
17
16
SYNCWT2
RW
RW
0
0
1
0
SYNCT0
RW
RW
0
0
Bit/Field
31:24
23:22
Name
reserved
SYNCWT5
Type
RO
RW
Reset
0x00
0x0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Synchronize GPTM 32/64-Bit Timer 5
The SYNCWT5 values are defined as follows:
Value Description
0x0 GPTM 32/64-Bit Timer 5 is not affected.
0x1 A timeout event for Timer A of GPTM 32/64-Bit Timer 5 is
triggered.
0x2 A timeout event for Timer B of GPTM 32/64-Bit Timer 5 is
triggered.
0x3 A timeout event for both Timer A and Timer B of GPTM 32/64-Bit
Timer 5 is triggered.
754
June 12, 2014
Texas Instruments-Production Data