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TM4C123GE6PZ Datasheet, PDF (1429/1445 Pages) Texas Instruments – Tiva™ TM4C123GE6PZ Microcontroller
Tiva™ TM4C123GE6PZ Microcontroller
24.15 Synchronous Serial Interface (SSI)
Table 24-34. SSI Characteristics
Parameter
No.
S1
Parameter Parameter Name
TCLK_PER
SSIClk cycle time, as mastera
SSIClk cycle time, as slaveb
Min
Nom Max
Unit
40
-
-
ns
150
-
-
ns
SSIClk high time, as master
S2
TCLK_HIGH SSIClk high time, as slave
20
-
-
ns
75
-
-
ns
SSIClk low time, as master
S3
TCLK_LOW SSIClk low time, as slave
20
-
-
ns
75
-
-
ns
S4
TCLKR
SSIClk rise timec
S5
TCLKF
SSIClk fall timec
1.25
-
-
ns
1.25
-
-
ns
S6
TTXDMOV Master Mode: Master Tx Data Output (to slave)
-
Valid Time from edge of SSIClk
-
15.7
ns
S7
TTXDMOH Master Mode: Master Tx Data Output (to slave)
0.31
-
-
ns
Hold Time from next SSIClk
S8
TRXDMS Master Mode: Master Rx Data In (from slave)
17.15
-
-
ns
setup time
S9
TRXDMH Master Mode: Master Rx Data In (from slave) hold
0
-
-
ns
time
S10
TTXDSOV Slave Mode: Master Tx Data Output (to Master)
-
Valid Time from edge of SSIClk
- 77.74d
ns
S11
TTXDSOH Slave Mode: Slave Tx Data Output (to Master)
55.5e
-
-
ns
Hold Time from next SSIClk
S12
TRXDSSU Slave Mode: Rx Data In (from master) setup time
0
-
-
ns
S13
TRXDSH
Slave Mode: Rx Data In (from master) hold time
51.55f
-
-
ns
a. In master mode, the system clock must be at least twice as fast as the SSIClk.
b. In slave mode, the system clock must be at least 12 times faster than the SSIClk.
c. Note that the delays shown are using 8-mA drive strength.
d. This MAX value is for the minimum TSYSCLK (12.5 ns). To find the MAX TTXDSOV value for a larger TSYSCLK, use the
equation: 4*TSYSCLK+27.74.
e. This MIN value is for the minimum slave mode TSYSCLK (12.5 ns). To find the MIN TTXDSOH value for a larger TSYSCLK,
use the equation: 4*TSYSCLK+5.50.
f. This MIN value is for the minimum slave mode TSYSCLK (12.5 ns). To find the MIN TRXDSH value for a larger TSYSCLK, use
the equation: 4*TSYSCLK+1.55.
June 12, 2014
Texas Instruments-Production Data
1429