TM4C123GE6PZ Datasheet, PDF (1026/1445 Pages) Texas Instruments – Tiva™ TM4C123GE6PZ Microcontroller

Inter-Integrated Circuit (I²C) Interface
Figure 16-7. High-Speed Data Format
SDA
SCL
Device-Specific
NAK
R/W
Address
Data
Note:
Standard (100 KHz) or Fast Mode (400 KHz)
High Speed
(3.3 Mbps)
High-Speed mode is 3.4 Mbps, provided correct system clock frequency is set and there is
appropriate pull strength on SCL and SDA lines.
16.3.3
Interrupts
The I²C can generate interrupts when the following conditions are observed:
■ Master transaction completed
■ Master arbitration lost
■ Master transaction error
■ Master bus timeout
■ Slave transaction received
■ Slave transaction requested
■ Stop condition on bus detected
■ Start condition on bus detected
The I²C master and I²C slave modules have separate interrupt signals. While both modules can
generate interrupts for multiple conditions, only a single interrupt signal is sent to the interrupt
controller.
16.3.3.1
I²C Master Interrupts
The I²C master module generates an interrupt when a transaction completes (either transmit or
receive), when arbitration is lost, or when an error occurs during a transaction. To enable the I²C
master interrupt, software must set the IM bit in the I²C Master Interrupt Mask (I2CMIMR) register.
When an interrupt condition is met, software must check the ERROR and ARBLST bits in the I²C
Master Control/Status (I2CMCS) register to verify that an error didn't occur during the last transaction
and to ensure that arbitration has not been lost. An error condition is asserted if the last transaction
wasn't acknowledged by the slave. If an error is not detected and the master has not lost arbitration,
the application can proceed with the transfer. The interrupt is cleared by writing a 1 to the IC bit in
the I²C Master Interrupt Clear (I2CMICR) register.
If the application doesn't require the use of interrupts, the raw interrupt status is always visible via
the I²C Master Raw Interrupt Status (I2CMRIS) register.
16.3.3.2 I²C Slave Interrupts
The slave module can generate an interrupt when data has been received or requested. This interrupt
is enabled by setting the DATAIM bit in the I²C Slave Interrupt Mask (I2CSIMR) register. Software
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June 12, 2014