DAC38RF80 Datasheet, PDF (74/152 Pages) Texas Instruments – Dual- or Single-Channel, Single-Ended or Differential-Output, 14-bit, 9-GSPS, RF-Sampling DAC with JESD204B Interface and On-Chip PLL

DAC38RF80, DAC38RF83, DAC38RF84
DAC38RF85, DAC38RF90, DAC38RF93
SLASEA3 – DECEMBER 2016
Register Maps (continued)
Table 41. Register Summary (continued)
Address
Reset
Acronym
0x65
0x0000
JESD_ ALM_L1
0x66
0x0000
JESD_ ALM_L2
0x67
0x0000
JESD_ALM_L3
0x68
0x0000
JESD_ALM_L4
0x69
0x0000
JESD_ALM_L5
0x6A
0x0000
JESD_ALM_L6
0x6B
0x0000
JESD_ALM_L7
0x6C
0x0000
ALM_SYSREF_PAP
0x6D
0x0000
ALM_CLKDIV1
0x6E-0x77
0x0000
Reserved
Miscellaneous Configuration Registers (PAGE_SET[1:0] = 00, PAGE_SET[2] = 1)
0x0A
0xFC03
CLK_CONFIG
0x0B
0x0022
SLEEP_CONFIG
0x0C
0xA002
CLK_OUT
0x0D
0xF000
DACFS
0x0E-0x0F
0x0000
Reserved
0x10
0x0000
LCMGEN
0x11
0x0000
LCMGEN_DIV
0x12
0x0000
LCMGEN_SPISYSREF
0x13-0x1A
0x0000
Reserved
0x1B
0x0000
DTEST
0x1C-0x22
0x0000
Reserved
0x23
0x03F3
SLEEP_CNTL
0x24
0x1000
SYSR_CAPTURE
0x25-0x30
0x0000
Reserved
0x31
0x0200
CLK_PLL_CFG
0x32
0x0308
PLL_CONFIG1
0x33
0x4018
PLL_CONFIG2
0x34
0x0000
LVDS_CONFIG
0x35
0x0018
PLL_FDIV
0x36-0x3A
0x0000
Reserved
0x3B
0x0002
SRDS_CLK_CFG
0x3C
0x8228
SRDS_PLL_CFG
0x3D
0x0088
SRDS_CFG1
0x3E
0x0909
SRDS_CFG2
0x3F
0x0000
SRDS_POL
0x40-0x75
0x0000
Reserved
0x76
0x0000
SYNCBOUT
Register Name
JESD Alarms for Lane 1
JESD Alarms for Lane 2
JESD Alarms for Lane 3
JESD Alarms for Lane 4
JESD Alarms for Lane 5
JESD Alarms for Lane 6
JESD Alarms for Lane 7
SYSREF and PAP Alarms
Clock Divider Alarms 1
Reserved
Clock Configuration
Sleep Configuration
Divided Output Clock Configuration
DAC Fullscale Current
Reserved
Internal sysref generator
Counter for internal sysref generator
SPI SYSREF for internal sysref generator
Reserved
Digital Test Signals
Reserved
Sleep Pin Control
SYSREF Capture Circuit Control
Reserved
Clock Input and PLL Configuration
PLL Configuration 1
PLL Configuration 2
LVDS Output Configuration
Fuse farm clock divider
Reserved
Serdes Clock Configuration
Serdes PLL Configuration
Serdes Configuration 1
Serdes Configuration 2
Serdes Polarity Control
Reserved
JESD204B SYNCB Output
www.ti.com
Section
8.5.60
8.5.61
8.5.62
8.5.63
8.5.64
8.5.65
8.5.66
8.5.67
8.5.68
8.5.69
8.5.70
8.5.71
8.5.72
8.5.73
8.5.74
8.5.75
8.5.76
8.5.77
8.5.78
8.5.79
8.5.80
8.5.81
8.5.82
8.5.83
8.5.84
8.5.85
8.5.86
8.5.87
8.5.88
8.5.89
74
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: DAC38RF80 DAC38RF83 DAC38RF84 DAC38RF85 DAC38RF90 DAC38RF93