DAC38RF80 Datasheet, PDF (123/152 Pages) Texas Instruments – Dual- or Single-Channel, Single-Ended or Differential-Output, 14-bit, 9-GSPS, RF-Sampling DAC with JESD204B Interface and On-Chip PLL

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DAC38RF80, DAC38RF83, DAC38RF84
DAC38RF85, DAC38RF90, DAC38RF93
SLASEA3 – DECEMBER 2016
8.5.75 SPI SYSREF for Internal SYSREF Generator Register (address = 0x12) [reset = 0x0000]
Figure 144. SPI SYSREF for Internal SYSREF Generator Register (LCMGEN_SPISYSREF)
15
14
13
12
11
10
9
8
0
0
0
0
0
0
0
x
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
0
0
0
0
1
1
0
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 116. LCMGEN_SPISYSREF Field Descriptions
Bit Field
15:1 Reserved
0
LCMGEN_SPI_SYSREF
Type
R/W
R/W
Reset
0x00
0
Description
Reserved
SPI SYSREF for the LCMGEN block
8.5.76 Digital Test Signals Register (address = 0x1B) [reset = 0x0000]
Figure 145. Digital Test Signals Register (DTEST)
15
14
13
12
11
10
9
8
0
0
0
0
0
0
0
x
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
0
0
0
1
1
0
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Bit
15
14:12
Field
Reserved
DTEST_LANE
11:8 DTEST
7:0 Reserved
Table 117. DTEST Field Descriptions
Type
R/W
R/W
Reset
0
000
R/W
0x0
R/W
0x00
Description
Reserved
Selects the lane to check for the signals selected by field
DTEST
Allows digital test signals to come out the ALARM pin.
0000 : Test disabled; normal ALARM pin function
0001 : SERDES lanes 0 – 3 PLL clock/80
0010 : SERDES lanes 4 – 7 PLL clock/80
0011 : TESTFAIL (lane selected by field DTEST_LANE)
0100 : SYNC (lane selected by field DTEST_LANE)
0101 : OCIP (lane selected by field DTEST_LANE)
0110 : EQUNDER (lane selected by field DTEST_LANE)
0111 : EQOVER (lane selected by field DTEST_LANE)
1000 – 1111 : not used
Reserved
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