DAC38RF80 Datasheet, PDF (125/152 Pages) Texas Instruments – Dual- or Single-Channel, Single-Ended or Differential-Output, 14-bit, 9-GSPS, RF-Sampling DAC with JESD204B Interface and On-Chip PLL

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DAC38RF80, DAC38RF83, DAC38RF84
DAC38RF85, DAC38RF90, DAC38RF93
SLASEA3 – DECEMBER 2016
8.5.78 SYSREF Capture Circuit Control Register (address = 0x24) [reset = 0x1000]
Figure 147. SYSREF Capture Circuit Control Register (SYSR_CAPTURE)
15
14
13
12
11
10
9
8
0
0
0
0
0
0
0
x
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
0
1
0
0
0
1
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 119. SYSR_CAPTURE Field Descriptions
Bit Field
15:14 SYSR_PHASE_WDW
13:12 SYSR_ALIGN_DLY
11
SYSR_STATUS_ENA
10:2 Reserved
1
SYSR_ALIGN_SYNC
0
SYSR_BYPS_ALIGN
Type
Reset
R/W
00
R/W
01
R/W
0
R/W
0x000
R/W
0
R/W
0
Description
sysref phase alignment tolerance window Centers sysref capture
window as follows:
00 = Centered on phase φ12 (**DEFAULT**)
01 = Centered on phase φ23
10 = Centered on phase φ34
11 = Centered on phase φ41
sysref alignment offset delay Optional alignment offset that
allows system designer to work around hardware (e.g. PCB)
alignment errors by letting him specify that the sysref pulse
should be treated as occurring one device clock earlier or later
than its observed position. Legal settings are as follows:
00 = Offset by -1 device clock cycles. Treat sysref as if it were
captured 1 cycle earlier.
01 = No offset (**DEFAULT**)
10 = Offset by +1 device clock cycles. Treat sysref as if it were
captured 1 cycle later.
11 = Reserved
Enable alignment status monitoring Enable logic that generates
sysref alignment status information and accumulates statistics
that can be read by the user.
0 = Disable sysref alignment status outputs (**DEFAULT**).
Used during normal operation.
1 = Enable sysref alignment status outputs. Used when
characterizing sysref capture timing.
Reserved
Write a ‘1’ to this bit to clear accumulated sysref align statistics
Bypass sysref alignment logic. Bypass the 4x oversampled
sysref alignment logic and instead capture the sysref signal
using the legacy implementation of a flip-flop clocked directly by
the rising edge of the device clock.
0 = Capture sysref using full-featured alignment circuit
(**DEFAULT**)
1 = Bypass sysref alignment logic
NOTE: When mem_sysref_bypass_align is enabled, the other
sysref alignment controls have no effect.
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