TMS320DM6446_15 Datasheet, PDF (73/227 Pages) Texas Instruments – Digital Media System-on-Chip

TMS320DM6446
www.ti.com
SPRS283H – DECEMBER 2005 – REVISED SEPTEMBER 2010
Table 3-13. DM6446 Multiplexed Peripheral Pins and Multiplexing Controls (continued)
MULTIPLEXED
PERIPHERALS
UART2, VPFE
PRIMARY
(DEFAULT)
FUNCTION
SECONDARY ⁽¹⁾
FUNCTION
VPFE:
UART2:
CI[5:4]/
UART_CTS2,
CCD_DATA[13:12] UART_RTS2
TERTIARY ⁽²⁾
FUNCTION
SECONDARY
REGISTER/PIN ⁽³⁾
CONTROL
PinMux1:UART2,
PinMux1:U2FLO
TERTIARY
REGISTER/PIN ⁽³⁾
CONTROL
3.5.3 Peripheral Selection After Device Reset
After device reset, the PINMUX0 and PINMUX1 registers are software programmable to allow multiplexing
of shared device pins between peripherals, as given in Section 2.7, Terminal Functions. Section 3.5.4
(PINMUX0 Register Description), Section 3.5.5 (PINMUX1 Register Description), and Section 3.5.6 (Pin
Multiplexing Register Field Details) identify the register settings necessary to configure specific multiplexed
functions and show the primary (default) function after reset.
3.5.4 PINMUX0 Register Description
The PINMUX0 pin multiplexing register controls which peripheral is given ownership over shared pins
among EMAC, CCD, LCD, RGB888, RGB666, ATA, VLYNQ, EMIFA, HPI, and GPIO peripherals. The
register format is shown in Figure 3-7 and bit field descriptions are given in Table 3-14. More details on
the PINMUX0 pin muxing fields are given in Section 3.5.6, Pin Multiplexing Register Field Details. A value
of '1' enables the secondary or tertiary pin function.
Figure 3-7. PINMUX0 Register⁽¹⁾
31
EMACEN
R/W-0
30
Rsvd
R/W-0
29
HPIEN
R/W-D
28
Rsvd
R-0
27
26
25
CFLDEN CWE LFLDEN
R/W-0 R/W-0 R/W-0
24
LOEEN
R/W-0
23
RGB888
R/W-0
22 21
18
RGB666 Reserved
R/W-0
R-0000
17
ATAEN
R/W-0
16
HDIREN
R/W-0
15
14
13 12
11
10
9
VLYNQEN VLSCREN VLYNQWD AECS5 AECS4
Reserved
54
0
AEAW
R/W-0
R/W-0
R/W-00
R/W-0 R/W-0
R-00000
R/W-LLLLL
LEGEND: R = Read; W = Write; L = pin state latched at reset rising edge; D = derived from pin states; -n = value after reset
(1) For proper DM6446 device operation, always write a value of '0' to RSV bit 30.
Name
EMACEN
HPIEN
CFLDEN
CWE
LFLDEN
LOEEN
RGB888
RGB666
ATAEN
HDIREN
VLYNQEN
VLSCREN
VLYNQWD
AECS5
Table 3-14. PINMUX0 Register Description
Description
Enable EMAC and MDIO function on default GPIO3V[0:16] pins.
Enable HPI module pins. Default value is derived from BTSEL[1:0] configuration inputs.
HPIEN is 1 when the BTSEL[1:0] = 10 and HPIEN is 0 (the default state) when
BTSEL[1:0] is 00, 01, or 11.
Enable CCD C_FIELD function on default GPIO[4] pin
Enable CCD C_WE function on default GPIO[1] pin
Enable LCD_FIELD function on default GPIO[3] pin
Enable LCD_OE function on default GPIO[0] pin
Enable VPBE RGB888 function on default GPIO[2:6, 46:47] pins
Enable VPBE RGB666 function on default GPIO[46:47] pins
Enable ATA function on default EMIFA and GPIO[52:53] pins and shared UART1 pins
Enable HDDIR function on default GPIO[42] pin
Enable VLYNQ function on default GPIO[9,10:17] pins
Enable VLYNQ SCRUN function on default GPIO[9] pin
VLYNQ data width selection. This expands the VLYNQ TXD[0:3] and RXD[0:3]
functions on default GPIO[10:17] pins.
Enable EMIFA EM_CS5 function on GPIO[8]
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Device Configurations
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