TMS320DM6446_15 Datasheet, PDF (185/227 Pages) Texas Instruments – Digital Media System-on-Chip

TMS320DM6446
www.ti.com
SPRS283H – DECEMBER 2005 – REVISED SEPTEMBER 2010
Address
0x01C6 41E0
0x01C6 41E4
0x01C6 41E8
0x01C6 41EC
0x01C6 41F0
0x01C6 41F4
0x01C6 41F8
0x01C6 41FC
0x01C6 4400
0x01C6 4401
0x01C6 4402
0x01C6 4404
0x01C6 4406
0x01C6 4408
0x01C6 440A
0x01C6 440B
0x01C6 440C
0x01C6 440E
0x01C6 440F
0x01C6 4410
0x01C6 4412
0x01C6 4414
0x01C6 4416
0x01C6 4418
0x01C6 441A
0x01C6 441A
0x01C6 441B
0x01C6 441B
0x01C6 441C
0x01C6 441D
Table 6-71. USB 2.0 Register Descriptions (continued)
Acronym
RCPPIDMASTATEW0
RCPPIDMASTATEW1
RCPPIDMASTATEW2
RCPPIDMASTATEW3
RCPPIDMASTATEW4
RCPPIDMASTATEW5
RCPPIDMASTATEW6
RCPPICOMPPTR
FADDR
POWER
INTRTX
INTRRX
INTRTXE
INTRRXE
INTRUSB
INTRUSBE
FRAME
INDEX
TESTMODE
TXMAXP
PERI_CSR0
HOST_CSR0
PERI_TXCSR
HOST_TXCSR
RXMAXP
PERI_RXCSR
HOST_RXCSR
COUNT0
RXCOUNT
HOST_TYPE0
HOST_TXTYPE
HOST_NAKLIMIT0
HOST_TXINTERVAL
HOST_RXTYPE
HOST_RXINTERVAL
Register Description
RX CPPI DMA State Word 0
RX CPPI DMA State Word 1
RX CPPI DMA State Word 2
RX CPPI DMA State Word 3
RX CPPI DMA State Word 4
RX CPPI DMA State Word 5
RX CPPI DMA State Word 6
RX CPPI Completion Pointer
Core Registers
Function Address Register
Power Management Register
Interrupt Register for Endpoint 0 plus TX Endpoints 1 to 4
Interrupt Register for RX Endpoints 1 to 4
Interrupt Enable Register for INTRTX
Interrupt Enable Register for INTRRX
Interrupt Register for Common USB Interrupts
Interrupt Enable Register for INTRUSB
Frame Number Register
Index register for selecting the endpoint status and control registers
Register to enable the USB 2.0 test modes
Maximum packet size for peripheral/host TX endpoint (Index register set to select
Endpoints 1 - 4 only)
Control Status register for Endpoint 0 in Peripheral mode. (Index register set to
select Endpoint 0)
Control Status register for Endpoint 0 in Host mode. (Index register set to select
Endpoint 0)
Control Status register for peripheral TX endpoint. (Index register set to select
Endpoints 1 - 4)
Control Status register for host TX endpoint. (Index register set to select
Endpoints 1 - 4)
Maximum packet size for peripheral/host RX endpoint (Index register set to select
Endpoints 1 - 4 only)
Control Status register for peripheral RX endpoint. (Index register set to select
Endpoints 1 - 4)
Control Status register for host RX endpoint. (Index register set to select
Endpoints 1 - 4)
Number of received bytes in Endpoint 0 FIFO. (Index register set to select
Endpoint 0)
Number of bytes in host RX endpoint FIFO. (Index register set to select
Endpoints 1 - 4)
Defines the speed of Endpoint 0
Sets the operating speed, transaction protocol and peripheral endpoint number
for the host TX endpoint. (Index register set to select Endpoints 1 - 4 only)
Sets the NAK response timeout on Endpoint 0. (Index register set to select
Endpoint 0)
Sets the polling interval for Interrupt/ISOC transactions or the NAK response
timeout on Bulk transactions for host TX endpoint. (Index register set to select
Endpoints 1 - 4 only)
Sets the operating speed, transaction protocol and peripheral endpoint number
for the host RX endpoint. (Index register set to select Endpoints 1 - 4 only)
Sets the polling interval for Interrupt/ISOC transactions or the NAK response
timeout on Bulk transactions for host RX endpoint. (Index register set to select
Endpoints 1 - 4 only)
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Peripheral and Electrical Specifications 185
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