TMS320DM6446_15 Datasheet, PDF (104/227 Pages) Texas Instruments – Digital Media System-on-Chip

TMS320DM6446
SPRS283H – DECEMBER 2005 – REVISED SEPTEMBER 2010
DM644x
www.ti.com
+1.8 V
EMI Filter
C1
0.1 µF
C2
0.01 µF
PLLV_DD18
PLL1
PLL2
Figure 6-13. PLL1 and PLL2 External Connection
The minimum CLKIN rise and fall times should also be observed. For the input clock timing requirements,
see Section 6.6.3, Clock PLL Electrical Data/Timing (Input and Output Clocks).
There is an allowable range for PLL multiplier (PLLM). There is a minimum and maximum operating
frequency for MXI/CLKIN, PLLOUT, and the device clocks (SYSCLKs). The PLL Controllers must be
configured not to exceed any of these constraints documented in this section (certain combinations of
external clock inputs, internal dividers, and PLL multiply ratios might not be supported).
Table 6-13. PLLC1 Clock Frequency Ranges
CLOCK SIGNAL NAME
MIN
MXI/CLKIN ⁽¹⁾
20
PLLOUT
At 1.2-V CV_DD
400
At 1.3-V CV_DD (-810 only)
400
-594 (commercial temp)
SYSCLK1 (CLKDIV1 Domain)
-810 (commercial temp)
A-513 (extended temp)
(1) MXI/CLKIN input clock is used for both PLL Controllers (PLLC1 and PLLC2).
MAX
30
600
810
600
810
513
UNIT
MHz
MHz
MHz
MHz
MHz
MHz
Table 6-14. PLLC2 Clock Frequency Ranges
CLOCK SIGNAL NAME
MIN
MXI/CLKIN ⁽¹⁾
20
PLLOUT
At 1.2-V CV_DD
400
At 1.3-V CV_DD (-810 only)
400
(1) MXI/CLKIN input clock is used for both PLL Controllers (PLLC1 and PLLC2).
MAX
30
900
900
UNIT
MHz
MHz
MHz
Both PLL1 and PLL2 have stabilization, lock, and reset timing requirements that must be followed.
The PLL stabilization time is the amount of time that must be allotted for the internal PLL regulators to
become stable after the PLL is powered up (after PLLCTL.PLLPWRDN bit goes through a 1-to-0
transition). The PLL should not be operated until this stabilization time has expired. This stabilization step
must be applied after these resets—a Power-on Reset, a Warm Reset, or a Max Reset, as the
PLLCTL.PLLPWRDN bit resets to a "1". For the PLL stabliziation time value, see Table 6-15.
The PLL reset time is the amount of wait time needed for the PLL to properly reset (writing PLLRST = 0)
before bringing the PLL out of reset (writing PLLRST = 1). For the PLL reset time value, see Table 6-15.
104 Peripheral and Electrical Specifications
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