TMS320DM6446_15 Datasheet, PDF (49/227 Pages) Texas Instruments – Digital Media System-on-Chip

TMS320DM6446
www.ti.com
SPRS283H – DECEMBER 2005 – REVISED SEPTEMBER 2010
Table 2-25. MMC/SD/SDIO Terminal Functions
SIGNAL
TYPE ⁽¹⁾
NAME
NO.
SD_CLK
SD_CMD
SD_DATA3
SD_DATA2
SD_DATA1
SD_DATA0
A9
O
B9 I/O/Z
C9 I/O/Z
D9 I/O/Z
E9 I/O/Z
D8 I/O/Z
OTHER ⁽²⁾
DV_DD33
DV_DD33
DV_DD33
DESCRIPTION
MMC/SD/SDIO
Data clock output SD_CLK
Bi-directional command IO SD_CMD
These pins are the nibble-wide bi-directional data bus SD_DATA[3:0].
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
(2) Specifies the operating I/O supply voltage for each signal
SIGNAL
NAME
EM_CS3
EM_BA[0]/
DA0/
HINT
EM_A[0]/
DA2/
HCNTL1/
GPIO53
EM_A[2]/
(CLE)/
HCNTL0
EM_A[1]/
(ALE)/
HHWIL
EM_R/W/
INTRQ/
HR/W
EM_CS2/
HCS
EM_WE
(WE)
(IOWR)/
DIOW/
HDS2
EM_OE/
(RE)/
(IORD)/
DIOR/
HDS1
EM_WAIT/
(RDY/BSY)/
IORDY/
HRDY
TYPE ⁽¹⁾
NO.
B1 I/O/Z
J3 I/O/Z
J4 I/O/Z
J1 I/O/Z
J2 I/O/Z
G3 I/O/Z
C2 I/O/Z
G2 I/O/Z
H4 I/O/Z
F1 I/O/Z
Table 2-26. HPI Terminal Functions
OTHER ^{(2) (3)}
DESCRIPTION
DV_DD18
DV_DD18
DV_DD18
DV_DD18
DV_DD18
DV_DD18
DV_DD18
Host-Port Interface (HPI)
For EMIFA, this pin is Chip Select 3 output.
In HPI mode this pin must be pulled high via an external 10-kΩ resistor.
This pin is multiplexed between EMIFA, ATA/CF, and HPI.
In HPI mode, it is the host interrupt output HINT.
This pin is multiplexed between EMIFA, ATA/CF, HPI, and GPIO.
For HPI, it is control input HCNTL1. The state of HCNTL1 and HCNTL0 determine
if address, data, or control information is being transmitted between an external
host and DM644X.
This pin is multiplexed between EMIFA (NAND/SmartMedia/xD), and HPI.
In HPI mode, it is control input HCNTL0. The state of HCNTL1 and HCNTL0
determine if address, data, or control information is being transmitted between an
external host and DM644X.
This pin is multiplexed between EMIFA (NAND/SmartMedia/xD), and HPI.
In HPI mode, it is Half-word identification input HHWIL.
This pin is multiplexed between EMIFA, ATA/CF, and HPI.
For HPI, it is the Host Read Write input HR/W. This signal is active high for reads
and low for writes.
This pin is multiplexed between EMIFA and HPI.
In HPI mode, this pin is HPI Active Low Chip Select input HCS.
DV_DD18
This pin is multiplexed between EMIFA (NAND/SmartMedia/xD), ATA/CF, and HPI.
For HPI, it is data strobe 2 input HDS2.
DV_DD18
This pin is multiplexed between EMIFA (NAND/SmartMedia/xD), ATA/CF, and HPI.
For HPI, it is data strobe 1 input HDS1.
IPU
DV_DD18
This pin is multiplexed between EMIFA (NAND/SmartMedia/xD), ATA/CF, and HPI.
For HPI, it is ready output HRDY.
(1) IPD = Internal pulldown, IPU = Internal pullup. (To pull up a signal to the opposite supply rail, a 1-kΩ resistor should be used.)
(2) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
(3) Specifies the operating I/O supply voltage for each signal
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