ADC12J1600_16 Datasheet, PDF (70/98 Pages) Texas Instruments – GSPS ADCs With Integrated DDC

ADC12J1600, ADC12J2700
SLAS969C – JANUARY 2014 – REVISED JULY 2015
7.6.1.6.1 Calibration Configuration 0 Register (address = 0x050) [reset = 0x06]
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Figure 87. Calibration Configuration 0 Register (CAL_CFG0)
7
6
RESERVED
R/W-00
5
4
TIME_STAMP_EN CALIBRATION_READ_WRITE_EN
R/W-0
R/W-0
3
CAL_SFT
R/W-0
Table 64. CAL_CFG0 Field Descriptions
2
1
0
RESERVED
R/W-110
Bit Field
7-
RESERVED
5
TIME_STAMP_EN
Type
R/W
R/W
Reset
00
0
4
CALIBRATION_READ_WRITE_EN R/W
0
3
CAL_SFT ⁽¹⁾
R/W
0
2-0 RESERVED
R/W
110
Description
Enables the capture of the external time stamp signal to allow
tracking of input signal.
Default: 0
Enables the scan register to read or write calibration vectors at
register 0x05A.
Default: 0
Software calibration bit. Set bit to initiate foreground calibration.
This bit is self-clearing.
This bit resets the calibration state machine. Most calibration
SPI registers are not synchronized to the calibration clock.
Changing them may corrupt the calibration state machine.
Always set CAL_SFT AFTER making any changes to the
calibration registers.
Default: 110
(1) IMPORTANT NOTE: Setting CAL_SFT can glitch internal state machines. The JESD_EN bit must be cleared and then set after setting
CAL_SFT.
7.6.1.6.2 Calibration Configuration 1 Register (address = 0x051) [reset = 0xF4]
Figure 88. Calibration Configuration 1 Register (CAL_CFG1)
7
6
5
4
3
2
1
0
RESERVED
LOW_SIG_EN
RESERVED
R/W-1
R/W-111
R/W-0100
Bit Field
7
RESERVED
6-4 LOW_SIG_EN
3-0 RESERVED
Table 65. CAL_CFG1 Field Descriptions
Type
R/W
R/W
Reset
1
111
R/W
0100
Description
Controls signal range optimization for calibration processes.
111: Calibration is optimized for lower amplitude input signals (<
–10dBFS).
000: Calibration is optimized for large (-1dBFS) input
signals.
Default: 111 but recommend 000 for large input signals.
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