ADC12J1600_16 Datasheet, PDF (1/98 Pages) Texas Instruments – GSPS ADCs With Integrated DDC

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ADC12J1600, ADC12J2700
SLAS969C – JANUARY 2014 – REVISED JULY 2015
ADC12Jxx00 12-Bit 1.6 or 2.7 GSPS ADCs With Integrated DDC
1 Features
•1 Excellent Noise and Linearity up to and beyond
F_IN = 3 GHz
• Configurable DDC
• Decimation Factors from 4 to 32 (Complex
Baseband Out)
• Bypass Mode for Full Nyquist Output Bandwidth
• Usable Output Bandwidth of 540 MHz at
4x Decimation and 2700 MSPS
• Usable Output Bandwidth of 320 MHz at
4x Decimation and 1600 MSPS
• Usable Output Bandwidth of 67.5 MHz at
32x Decimation and 2700 MSPS
• Usable Output Bandwidth of 40 MHz at
32x Decimation and 1600 MSPS
• Low Pin-Count JESD204B Subclass 1 Interface
• Automatically Optimized Output Lane Count
• Embedded Low Latency Signal Range Indication
• Low Power Consumption
• Key Specifications
– Max Sampling Rate: 1600 or 2700 MSPS
– Min Sampling Rate: 1000 MSPS
– DDC Output Word Size: 15-Bit Complex (30
bits total)
– Bypass Output Word Size: 12-Bit Offset Binary
– Noise Floor: –147.3 dBFS/Hz (ADC12J2700)
– Noise Floor: –145 dBFS/Hz (ADC12J1600)
– IMD3: −64 dBc (F_IN = 2140 MHz ± 30 MHz at
−13 dBFS)
– FPBW (–3 dB): 3.2 GHz
– Peak NPR: 46 dB
– Supply Voltages: 1.9 V and 1.2 V
– Power Consumption
– Bypass (2700 MSPS): 1.8 W
– Bypass (1600 MSPS): 1.6 W
– Power Down Mode: <50 mW
2 Applications
• Wireless Infrastructure
• RF-Sampling Software Defined Radio
• Wideband Microwave Backhaul
• Military Communications
• SIGINT
• RADAR and LIDAR
• DOCSIS / Cable Infrastructure
• Test and Measurement
3 Description
The ADC12J1600 and ADC12J2700 devices are
wideband sampling and digital tuning devices. Texas
Instruments' giga-sample analog-to-digital converter
(ADC) technology enables a large block of frequency
spectrum to be sampled directly at RF. An integrated
DDC (Digital Down Converter) provides digital filtering
and down-conversion. The selected frequency block
is made available on a JESD204B serial interface.
Data is output as baseband 15-bit complex
information for ease of downstream processing.
Based on the digital down-converter (DDC)
decimation and link output rate settings, this data is
output on 1 to 5 lanes of the serial interface.
A DDC bypass mode allows the full rate 12-bit raw
ADC data to also be output. This mode of operation
requires 8 lanes of serial output.
The ADC12J1600 and ADC12J2700 devices are
available in a 68-pin VQFN package. The device
operates over the Industrial (–40°C ≤ T_A ≤ 85°C)
ambient temperature range.
Device Information⁽¹⁾
PART NUMBER
PACKAGE
BODY SIZE (NOM)
ADC12J1600
VQFN (68)
10.00 mm × 10.00 mm
ADC12J2700
VQFN (68)
10.00 mm × 10.00 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Bypass — Spectral Response
ƒ_S = 2.7 GHz, F_IN = 1897 MHz at –1 dBFS
0
-20
-40
-60
-80
-100
0
225
450
675
900
1125
1350
Frequency (MHz)
C001
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.