ADC12J1600_16 Datasheet, PDF (13/98 Pages) Texas Instruments – GSPS ADCs With Integrated DDC

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ADC12J1600, ADC12J2700
SLAS969C – JANUARY 2014 – REVISED JULY 2015
Electrical Characteristics (continued)
Unless otherwise noted, these specifications apply for V_(VA12) = V_(VD12) = 1.2 V, V_(VA19) = 1.9 V, VIN full scale range at default
setting (725 mV_PP), VIN = –1 dBFS, differential AC-coupled sinewave input clock, ƒ_(DEVCLK) = 2.7 or 1.6 GHz at 0.5 V_PP with
50% duty cycle, R_(RBIAS) = 3.3 kΩ ±0.1%, after a foreground (FG) mode calibration with timing calibration enabled. Typical
values are at T_A = 25°C.⁽¹⁾⁽²⁾
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
NSD
Noise spectral density,
average NSD across Nyquist
bandwidth
12-bit DDC bypass mode, ADC12J1600,
ƒ_(DEVCLK) = 1.6 GHz
50-Ω AC-coupled terminated input
F_IN = 600 MHz, –1 dBFS
–145
–146.8
–143.9
–145.7
dBFS/Hz
dBm/Hz
dBFS/Hz
dBm/Hz
DECIMATE-BY-8 MODE, ADC12J2700, ƒ_(DEVCLK) = 2.7 GHz
SNR
Signal-to-noise ratio,
integrated across DDC output
bandwidth
Interleaving spurs included
F_IN = 600 MHz, –1 dBFS, decimate-by-8
mode
Calibration = BG
F_IN = 2400 MHz, –1 dBFS, Decimate-by-8 mode
SINAD
Signal-to-noise and distortion
ratio, integrated across DDC
output bandwidth
Interleaving spurs included
F_IN = 600 MHz, –1 dBFS, decimate-by-8
mode
Calibration = BG
F_IN = 2400 MHz, –1 dBFS, decimate-by-8 mode
ENOB
Effective number of bits,
integrated across DDC output
bandwidth
Interleaving spurs included
F_IN = 600 MHz, –1 dBFS, decimate-by-8
mode
Calibration = BG
F_IN = 2400 MHz, –1 dBFS, decimate-by-8 mode
SFDR
Spurious-free dynamic range F_IN = 600 MHz, –1 dBFS, decimate-by-8
Interleaving spurs included mode
Calibration = BG
62.8
62.7
dBFS
53.3
62.8
62.7
dBFS
53.3
10.1
10.1
Bits
8.6
75.9
dBFS
74.7
ƒ_S/2
Interleaving offset spur at ½ F_IN = 600 MHz, –1 dBFS, decimate-by-8
sampling rate⁽³⁾
mode
Calibration = BG
–73
dBFS
–72
ƒ_S/4
Interleaving offset spur at ¼ F_IN = 600 MHz, –1 dBFS, decimate-by-8
sampling rate⁽³⁾
mode
Calibration = BG
–70
dBFS
–70
ƒ_S/2 – F_IN
Interleaving spur at ½
sampling rate – input
frequency⁽³⁾
F_IN = 600 MHz, –1 dBFS, decimate-by-8
mode
Calibration = BG
–80
dBFS
–79
ƒ_S/4 + F_IN
Interleaving spur at ¼
sampling rate + input
frequency⁽³⁾
F_IN = 600 MHz, –1 dBFS, decimate-by-8
mode
Calibration = BG
–73
dBFS
–70
ƒ_S/4 – F_IN
Interleaving spur at ¼
sampling rate – input
frequency⁽³⁾
F_IN = 600 MHz, –1 dBFS, decimate-by-8
mode
Calibration = BG
–77
dBFS
–77
THD
Total harmonic distortion⁽³⁾
F_IN = 600 MHz, –1 dBFS, decimate-by-8
mode
calibration = BG
–70
–71
dBFS
HD2
F_IN = 2400 MHz, –1 dBFS, decimate-by-8 mode
F_IN = 600 MHz, –1 dBFS, decimate-by-8
Second harmonic distortion^{(3) mode}
Calibration = BG
–65
–78
–76
dBFS
HD3
Third harmonic distortion⁽³⁾
F_IN = 2400 MHz, –1 dBFS, decimate-by-8 mode
F_IN = 600 MHz, –1 dBFS, decimate-by-8
mode
Calibration = BG
–67
–74
–81
dBFS
F_IN = 2400 MHz, –1 dBFS, decimate-by-8 mode
DECIMATE-BY-8 MODE, ADC12J1600, ƒ_(DEVCLK) = 1.6 GHz
SNR
Signal-to-noise ratio,
integrated across DDC output
bandwidth
Interleaving spurs included
F_IN = 600 MHz, –1 dBFS, decimate-by-8
mode
Calibration = BG
F_IN = 2400 MHz, –1 dBFS, decimate-by-8 mode
SINAD
Signal-to-noise and distortion
ratio, integrated across DDC
output bandwidth
Interleaving spurs included
F_IN = 600 MHz, –1 dBFS, decimate-by-8
mode
Calibration = BG
F_IN = 2400 MHz, –1 dBFS, decimate-by-8 mode
ENOB
Effective number of bits,
integrated across DDC output
bandwidth
Interleaving spurs included
F_IN = 600 MHz, –1 dBFS, decimate-by-8
mode
Calibration = BG
F_IN = 2400 MHz, –1 dBFS, decimate-by-8 mode
SFDR
Spurious-free dynamic range F_IN = 600 MHz, –1 dBFS, decimate-by-8
Interleaving Spurs Included mode
Calibration = BG
–73
63.5
63.4
dBFS
55.8
63.5
63.4
dBFS
55.8
10.3
10.2
Bits
9.0
76.2
dBFS
76.7
ƒ_S/2
Interleaving offset spur at ½ F_IN = 600 MHz, –1 dBFS, decimate-by-8
sampling rate⁽³⁾
mode
Calibration = BG
–73
dBFS
–72
(3) Magnitude of reported tones in output spectrum of ADC core. This tone will only be present in the DDC output for specific Decimation
and NCO settings. Careful frequency planning can be used to intentionally place unwanted tones outside the DDC output spectrum.
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