TLC6C598-Q1_16 Datasheet, PDF (7/24 Pages) Texas Instruments – Power Logic 8-Bit Shift Register LED Driver

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TLC6C598-Q1
SLIS142D – DECEMBER 2012 – REVISED SEPTEMBER 2016
6.8 Timing Waveforms
Figure 1 shows the SER IN to SER OUT waveform. The output signal appears on the falling edge of the shift
register clock (SRCK) because there is a phase inverter at SER OUT (see Figure 13). As a result, it takes seven
and a half periods of SRCK for data to transfer from SER IN to SER OUT.
8
7
6
5
4
3
2
1
SRCK
SER IN
CLR 1
SER OUT 0
Figure 1. SER IN to SER OUT Waveform
Figure 2 shows the switching times and voltage waveforms. Tests for all these parameters took place using the
test circuit shown in Figure 11.
G
Output
SRCK
SER IN
50%
t_PLH
10%
90%
t_r
50%
50%
t_PHL
90%
t_su
t_h
50%
50%
t_w
Switching Times, Input Setup and Hold Waveforms
5V
10%
t_f
0V
10 V
0.5 V
5V
0V
5V
0V
SRCK
50%
t_pd
50%
t_pd
SER OUT
50%
50%
SER OUT Propagation Delay Waveform
Figure 2. Switching Times and Voltage Waveforms
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