LP2997 Datasheet, PDF (7/21 Pages) National Semiconductor (TI) – DDR-II Termination Regulator

LP2997
www.ti.com
SNVS295F – MAY 2004 – REVISED APRIL 2013
OUTPUT CAPACITOR
The LP2997 has been designed to be insensitive of output capacitor size or ESR (Equivalent Series Resistance).
This allows the flexibility to use any capacitor desired. The choice for output capacitor will be determined solely
on the application and the requirements for load transient response of V_TT. As a general recommendation the
output capacitor should be sized above 100 µF with a low ESR for SSTL applications with DDR-SDRAM. The
value of ESR should be determined by the maximum current spikes expected and the extent at which the output
voltage is allowed to droop. Several capacitor options are available on the market and a few of these are
highlighted below:
AL - It should be noted that many aluminum electrolytics only specify impedance at a frequency of 120 Hz, which
indicates they have poor high frequency performance. Only aluminum electrolytics that have an impedance
specified at a higher frequency (100 kHz) should be used for the LP2997. To improve the ESR several AL
electrolytics can be combined in parallel for an overall reduction. An important note to be aware of is the extent
at which the ESR will change over temperature. Aluminum electrolytic capacitors can have their ESR rapidly
increase at cold temperatures.
Ceramic - Ceramic capacitors typically have a low capacitance, in the range of 10 to 100 µF range, but they have
excellent AC performance for bypassing noise because of very low ESR (typically less than 10 mΩ). However,
some dielectric types do not have good capacitance characteristics as a function of voltage and temperature.
Because of the typically low value of capacitance it is recommended to use ceramic capacitors in parallel with
another capacitor such as an aluminum electrolytic. A dielectric of X5R or better is recommended for all ceramic
capacitors.
Hybrid - Several hybrid capacitors such as OS-CON and SP are available from several manufacturers. These
offer a large capacitance while maintaining a low ESR. These are the best solution when size and performance
are critical, although their cost is typically higher than any other capacitors.
Thermal Dissipation
Since the LP2997 is a linear regulator any current flow from V_TT will result in internal power dissipation
generating heat. To prevent damaging the part from exceeding the maximum allowable junction temperature,
care should be taken to derate the part dependent on the maximum expected ambient temperature and power
dissipation. The maximum allowable internal temperature rise (T_Rmax) can be calculated given the maximum
ambient temperature (T_Amax) of the application and the maximum allowable junction temperature (T_Jmax).
T_Rmax = T_Jmax − T_Amax
(1)
From this equation, the maximum power dissipation (P_Dmax) of the part can be calculated:
P_Dmax = T_Rmax / θ_JA
(2)
The θ_JA of the LP2997 will be dependent on several variables: the package used; the thickness of copper; the
number of vias and the airflow. For instance, the θ_JA of the SOIC-8 is 163°C/W with the package mounted to a
standard 8x4 2-layer board with 1oz. copper, no airflow, and 0.5W dissipation at room temperature. This value
can be reduced to 151.2°C/W by changing to a 3x4 board with 2 oz. copper that is the JEDEC standard.
Figure 13 shows how the θ_JA varies with airflow for the two boards mentioned.
180
170
160
150
140
130
120
110
100
90
80
0
SOP Board
JEDEC Board
200 400 600 800 1000
AIRFLOW (Linear Feet per Minute)
Figure 13. θ_JA vs Airflow (SOIC-8)
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