LP2997 Datasheet, PDF (18/21 Pages) National Semiconductor (TI) – DDR-II Termination Regulator

DDA0008A
EXAMPLE BOARD LAYOUT
PowerPAD^TM SOIC - 1.7 mm max height
PLASTIC SMALL OUTLINE
8X (1.55)
1
8X (0.6)
SYMM
6X (1.27)
4
(R0.05) TYP
( 0.2) TYP
VIA
(2.95)
NOTE 9
(2.34)
SOLDER MASK
OPENING
SOLDER MASK
DEFINED PAD
SEE DETAILS
8
SYMM
(1.3) TYP
(5.4)
LAND PATTERN EXAMPLE
SCALE:10X
(2.34)
(1.3)
TYP
SOLDER MASK
OPENING
(4.9)
NOTE 9
5
METAL COVERED
BY SOLDER MASK
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4218825/A 05/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Size of metal pad may vary due to creepage requirement.
10. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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