LP2997 Datasheet, PDF (2/21 Pages) National Semiconductor (TI) – DDR-II Termination Regulator

LP2997
SNVS295F – MAY 2004 – REVISED APRIL 2013
Connection Diagram
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GND ¹
SD ²
VSENSE ³
VREF ⁴
GND
8 VTT
7 PVIN
6 _AVIN
5 _VDDQ
Figure 2. SO PowerPAD-8 Layout
See Package Number DDA (R-PDSO-G8)
GND ¹
SD ²
VSENSE ³
VREF ⁴
8 VTT
7 PVIN
6 _AVIN
5 _VDDQ
Figure 3. SOIC-8 Layout
See Package Number D0008A
SOIC-8 Pin or
SO PowerPAD-8 Pin
1
2
3
4
5
6
7
8
Name
GND
SD
VSENSE
VREF
VDDQ
AVIN
PVIN
VTT
EP
PIN DESCRIPTIONS
Function
Ground
Shutdown
Feedback pin for regulating V_TT.
Buffered internal reference voltage of V_DDQ/2
Input for internal reference equal to V_DDQ/2
Analog input pin
Power input pin
Output voltage for connection to termination resistors
Exposed pad thermal connection Connect to Ground
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings⁽¹⁾⁽²⁾
AVIN to GND
PVIN to GND
VDDQ ⁽³⁾
Storage Temp. Range
Junction Temperature
Lead Temperature (Soldering, 10 sec)
SOIC-8 Thermal Resistance (θ_JA)
SO PowerPAD-8 Thermal Resistance (θ_JA)
Minimum ESD Rating⁽⁴⁾
−0.3V to +6V
-0.3V to AVIN
−0.3V to +6V
−65°C to +150°C
150°C
260°C
151°C/W
43°C/W
1kV
(1) Absolute maximum ratings indicate limits beyond which damage to the device may occur. Operating range indicates conditions for which
the device is intended to be functional, but does not ensure specific performance limits. For specific specifications and test conditions
see Electrical Characteristics. The specified specifications apply only for the test conditions listed. Some performance characteristics
may degrade when the device is not operated under the listed test conditions.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
(3) VDDQ voltage must be less than 2 x (AVIN - 1) or 6V, whichever is smaller.
(4) The human body model is a 100pF capacitor discharged through a 1.5kΩ resistor into each pin.
Operating Range
Junction Temp. Range⁽¹⁾
AVIN to GND
0°C to +125°C
2.2V to 5.5V
(1) At elevated temperatures, devices must be derated based on thermal resistance. The device in the SOIC-8 package must be derated at
θ_JA = 151.2° C/W junction to ambient with no heat sink.
2
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