DS96F173M_13 Datasheet, PDF (7/12 Pages) Texas Instruments – DS96F173M/DS96F175C/DS96F175M EIA-485/EIA-422 Quad Differential Receivers

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MIL-STD-883C
Switching Characteristics
V_CC = 5.0V
Symbol
Parameter
Conditions
t_PLH
t_PHL
t_ZH
t_ZL
t_HZ
t_LZ
|t_PLH–t_PHL|
Propagation Delay Time, Low to
High Level Output
Propagation Delay Time, High to
Low Level Output
Output Enable Time to High Level
Output Enable Time to Low Level
Output Disable Time from High
Level
Output Disable Time from Low
Level
Pulse Width Distortion (SKEW)
V_ID = −2.5V to +2.5V,
C_L = 15 pF, See Figure 7
V_CM = 0V
C_L = 15 pF, See Figure 8
C_L = 15 pF, See Figure 9
C_L = 5.0 pF, See Figure 8 ⁽¹⁾
C_L = 20 pF, See Figure 8 ⁽¹⁾
C_L = 5.0 pF, See Figure 9
See Figure 7
(1) Testing at 20 pF assures conformance to 5 pF specification.
DS96F173M/DS96F175C/DS96F175M
SNOSC40F – JULY 2000 – REVISED APRIL 2013
T_A = 25°C T_A = −55°C
Typ Max
Max
T_A = 125°C Units
Max
15 22
30
30
ns
15 22
30
12 16
27
13 18
27
14 20
27
14 30
37
14 18
30
1
3
5.0
30
ns
27
ns
27
ns
27
ns
37
ns
30
ns
5.0
ns
Connection Diagrams
Figure 1. DS96F173 (Top View)⁽²⁾
16-Lead Ceramic Dual-In-Line CDIP Package
Package Number NFE
Figure 2. DS96F175 (Top View)⁽²⁾
16-Lead Ceramic Dual-In-Line CDIP Package
Package Number NFE
(2) DS96F173 with active high and active low Enables are
shown. DS96F175 has active high Enable only.
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