DS90CR563_11 Datasheet, PDF (7/14 Pages) Texas Instruments – LVDS 18-Bit Color Flat Panel Display (FPD) Link- 65 MHz

AC Timing Diagrams (Continued)
FIGURE 2. “16 Grayscale” Test Pattern
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Note 7: The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O and CMOS/TTL I/O.
Note 8: The 16 grayscale test pattern tests device power consumption for a “typical” LCD display pattern. The test pattern approximates signal switching needed
to produce groups of 16 vertical stripes across the display.
Note 9: Figure 1 and Figure 2 show a falling edge data strobe (TxCLK IN/RxCLK OUT).
Note 10: Recommended pin to signal mapping. Customer may choose to define differently.
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FIGURE 3. DS90CR563 (Transmitter) LVDS Output Load and Transition Times
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FIGURE 4. DS90CR564 (Receiver) CMOS/TTL Output Load and Transition Times
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FIGURE 5. DS90CR563 (Transmitter) Input Clock Transition Time
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