DS90CR563_11 Datasheet, PDF (5/14 Pages) Texas Instruments – LVDS 18-Bit Color Flat Panel Display (FPD) Link- 65 MHz

Electrical Characteristics (Continued)
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol
Parameter
Conditions
TRANSMITTER SUPPLY CURRENT
I_CCTZ Transmitter Supply Current,
Power Down
Power Down = Low
RECEIVER SUPPLY CURRENT
I_CCRW Receiver Supply Current,
Worst Case
C_L = 8 pF,
Worst Case Pattern
(Figures 1, 4)
f = 32.5 MHz
f = 37.5 MHz
f = 65 MHz
I_CCRG Receiver Supply Current,
16 Grayscale
C_L = 8 pF,
16 Grayscale Pattern
(Figures 2, 4)
f = 32.5 MHz
f = 37.5 MHz
f = 65 MHz
I_CCRZ Receiver Supply Current,
Power Down
Power Down = Low
Min Typ Max Units
1
25 µA
64 77 mA
70 85 mA
110 140 mA
35 55 mA
37 55 mA
55 67 mA
1
10 µA
Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device
should be operated at these limits. The tables of “Electrical Characteristics” specify conditions for device operation.
Note 2: Typical values are given for V_CC = 5.0V and T_A = +25˚C.
Note 3: Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground unless otherwise speci-
fied (except V_OD and ∆V _OD).
Note 4: ESD Rating: HBM (1.5 kΩ, 100 pF)
PLL V_CC ≥ 1000V
All other pins ≥ 2000V
EIAJ (0Ω, 200 pF) ≥ 150V
Transmitter Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol
LLHT
LHLT
TCIT
TCCS
TCCD
TCIP
TCIH
TCIL
TSTC
THTC
TPDD
TPLLS
TPPos0
Parameter
LVDS Low-to-High Transition Time (Figure 3)
LVDS High-to-Low Transition Time (Figure 3)
TxCLK IN Transition Time (Figure 5)
TxOUT Channel-to-Channel Skew (Note 5) (Figure 6)
TxCLK IN to TxCLK OUT Delay @ 25˚C, V_CC = 5.0V
(Figure 9)
TxCLK IN Period (Figure 7)
TxCLK IN High Time (Figure 7)
TxCLK IN Low Time (Figure 7)
TxIN Setup to TxCLK IN (Figure 7)
TxIN Hold to TxCLK IN (Figure 7)
Transmitter Powerdown Delay (Figure 18)
Transmitter Phase Lock Loop Set (Figure 11)
Transmitter Output Pulse Position 0 (Figure 13)
f = 65 MHz
Min
3.5
15
0.35T
0.35T
5
2.5
−0.30
TPPos1 Transmitter Output Pulse Position 1
1.70
TPPos2
TPPos3
TPPos4
TPPos5
TPPos6
Transmitter Output Pulse Position 2
Transmitter Output Pulse Position 3
Transmitter Output Pulse Position 4
Transmitter Output Pulse Position 5
Transmitter Output Pulse Position 6
3.60
5.90
8.30
10.40
12.70
Note 5: This limit based on bench characterization.
Typ
0.75
0.75
T
0.5T
0.5T
3.5
1.5
0
1/7 T_clk
2/7 T_clk
3/7 T_clk
4/7 T_clk
5/7 T_clk
6/7 T_clk
Max
Units
1.5
ns
1.5
ns
8
ns
350
ps
8.5
ns
50
ns
0.65T
ns
0.65T
ns
ns
ns
100
ns
10
ms
0.30
ns
2.50
ns
4.50
ns
6.75
ns
9.00
ns
11.10
ns
13.40
ns
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