DS90CR563_11 Datasheet, PDF (10/14 Pages) Texas Instruments – LVDS 18-Bit Color Flat Panel Display (FPD) Link- 65 MHz

AC Timing Diagrams (Continued)
FIGURE 13. Transmitter LVDS Output Pulse Position Measurement
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SW — Setup and Hold Time (Internal Data Sampling Window)
TCCS — Transmitter Output Skew
RSKM ≥ Cable Skew (type, length) + Source Clock Jitter (cycle to cycle)
Cable Skew — typically 10 ps–40 ps per foot
FIGURE 14. Receiver LVDS Input Skew Margin
FIGURE 15. Seven Bits of LVDS in One Clock Cycle
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