DRV8823_16 Datasheet, PDF (7/32 Pages) Texas Instruments – 4-Bridge Serial Interface Motor Driver

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6.6 Timing Requirements
over operating free-air temperature range (unless otherwise noted)
NO.
1 t_CYC
2 t_CLKH
3 t_CLKL
4
t_SU(SDATA)
5
t_H(DATA)
6
t_SU(SCS)
7
t_H(SCS)
Clock cycle time
Clock high time
Clock low time
Setup time, SDATA to SCLK
Hold time, SDATA to SCLK
Setup time, SCS to SCLK
Hold time, SCS to SCLK
DRV8823
SLVS913E – JANUARY 2009 – REVISED JANUARY 2016
MIN
MAX UNIT
62
ns
25
ns
25
ns
5
ns
1
ns
5
ns
1
ns
6.7 Dissipation Ratings
BOARD
Low-K ⁽¹⁾
Low-K ⁽²⁾
High-K ⁽³⁾
High-K ⁽⁴⁾
PACKAGE
DCA
R_θJA
75.7°C/W
32°C/W
30.3°C/W
22.3°C/W
DERATING FACTOR
ABOVE T_A = 25°C
13.2 mW/°C
31.3 mW/°C
33 mW/°C
44.8 mW/°C
T_A < 25°C
1.65 W
3.91 W
4.13 W
5.61 W
T_A = 70°C
1.06 W
2.50 W
2.48 W
3.59 W
T_A = 85°C
0.86 W
2.03 W
2.15 W
2.91 W
(1) The JEDEC low-K board used to derive this data was a 76-mm × 114-mm, 2-layer, 1.6-mm thick PCB with no backside copper.
(2) The JEDEC low-K board used to derive this data was a 76-mm × 114-mm, 2-layer, 1.6-mm thick PCB with 25-cm², 2-oz copper on back
side.
(3) The JEDEC high-K board used to derive this data was a 76-mm × 114-mm, 4-layer, 1.6-mm thick PCB with no backside copper and
solid 1-oz internal ground plane.
(4) The JEDEC high-K board used to derive this data was a 76-mm × 114-mm, 4-layer, 1.6-mm thick PCB with 25-cm², 1-oz copper on
backside and solid 1-oz internal ground plane.
1
SCLK
SDATA
2
3
Data
Invalid
4
5
SCS
6
7
Figure 1. Timing Diagram
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