DRV8823_16 Datasheet, PDF (15/32 Pages) Texas Instruments – 4-Bridge Serial Interface Motor Driver

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DRV8823
SLVS913E – JANUARY 2009 – REVISED JANUARY 2016
The state of the xDECAY bits in the serial interface registers selects whether the device is in slow-decay or
mixed-decay mode. If the xDECAY bit is 0,the device selects slow decay. If the xDECAY bit is 1, the device
selects mixed decay.
7.4.5 Protection Circuits
The DRV8823 is fully protected against undervoltage, overcurrent, and overtemperature events.
7.4.5.1 OCP
All of the drivers in DRV8823 are protected with an OCP circuit.
The OCP circuit includes an analog current limit circuit, which acts by removing the gate drive from each output
FET if the current through it exceeds a preset level. This circuit limits the current to a level that is safe to prevent
damage to the FET.
A digital circuit monitors the analog current limit circuits. If any analog current limit condition exists for longer than
a preset period, all drivers in the device are disabled.
The device is re-enabled upon the removal and re-application of power at the VM pins.
7.4.5.2 Thermal Shutdown (TSD)
If the die temperature exceeds safe limits, all drivers in the device are shut down.
The device remains disabled until the die temperature has fallen to a safe level. After the temperature has fallen,
the device may be re-enabled upon the removal and re-application of power at the VM pin.
7.4.5.3 Undervoltage Lockout (UVLO)
If at any time the voltage on the VM pins falls below the UVLO threshold voltage, all circuitry in the device is
disabled. Operation resumes when VM rises above the UVLO threshold. The indexer logic is reset to its initial
condition in the event of an UVLO.
7.4.5.4 Shoot-Through Current Prevention
The gate drive to each FET in the H-bridge is controlled to prevent any cross-conduction (shoot through current)
during transitions.
7.4.6 Serial Data Transmission
Data transfers consist of sixteen bits of serial data, shifted into the SDATA pin LSB first.
On serial writes to DRV8823, additional clock edges following the final data bit continue to shift data bits into the
data register; therefore, the last 16 bits presented are latched and used.
Select one of two registers by setting bits in an address field in the four upper bits in the serial data transferred
(ADDR in Table 3 and Table 4). One 16-bit register is used to control motor 1 (bridges A and B), and a second
16-bit register is used to control motor 2 (bridges C and D).
Data can only be transferred into the serial interface if the SCS input pin is active high.
Data is initially clocked into a temporary holding register. This data is latched into the motor driver on the rising
edge of the SSTB pin. If the SSTB pin is tied high at all times, the data is latched in after all 16 bits have been
transferred.
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