DDC316_17 Datasheet, PDF (7/28 Pages) Texas Instruments – 16-Channel, Current-Input Analog-to-Digital Converter

DDC316
www.ti.com......................................................................................................................................................... SBAS370A – MARCH 2008 – REVISED APRIL 2009
CLK
DIN_CFG
DVALID
DCLK
DOUT1
t_SC
1
0
1
0
CFG
Bit 15
t_HC
CFG
Bit 0
t_DVC
t_DCDV
t_DVDO
CFG
Bit 15
t_DOPD
Figure 2. Configuration Register Read/Write Timing
TIMING REQUIREMENTS FOR Figure 2
At T_A = 0°C to +70°C and DVDD = 3.0V to 3.6V, unless otherwise noted.
SYMBOL
DESCRIPTION
MIN
TYP
MAX
t_SC
Valid DIN_CFG to CLK falling edge; setup time
1
t_HC
Valid DIN_CFG to CLK falling edge; hold time
3
t_DVC(1) Delay of DVALID from falling edge of CLK
t_DCDV(1) Falling edge of first DCLK to rising edge of DVALID
t_DVDO(1) Delay from DVALID falling edge to valid CFG bit 15 on DOUT1
t_DOPD(1) Propagation delay from the falling edge of DCLK to valid DOUT1
t_DOHD ⁽¹⁾
Hold time during which previous DOUT1 is valid after falling edge of
DCLK
5
12
12
18
19
6
10
21
(1) Output load = 100kΩ || 10pF
t_DOHD
CFG
Bit 0
UNIT
ns
ns
ns
ns
ns
ns
ns
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