DDC316_17 Datasheet, PDF (14/28 Pages) Texas Instruments – 16-Channel, Current-Input Analog-to-Digital Converter

DDC316
SBAS370A – MARCH 2008 – REVISED APRIL 2009......................................................................................................................................................... www.ti.com
MINIMUM INTEGRATION TIME
The minimum integration time of the DDC316 is set
by the master clock (CLK) and the HI_SPEED bit, as
shown in Table 3. The integration time specification
must always be met for both side A and side B
integrations (t_INTA and t_INTB). Failure to meet
integration time specifications gives invalid
conversion results.
Table 3. Minimum Integration Times
HI_SPEED
VALID
BIT
RESOLUTIONS
0
12-bit only
1
12-bit to 16-bit
MINIMUM INTEGRATION TIME
(MINIMUM t_INT)
400 t_CLK
10µs
periods (for CLK = 40MHz)
800 t_CLK
20µs
periods (for CLK = 40MHz)
When operating with the HI_SPEED bit set to 0, the
DDC316 operates internally at a higher speed and
the performance is reduced to fundamentally 12 bits.
It is recommended, therefore, that the RES[1:0] bits
should be set to 12-bit resolution when HI_SPEED =
0. This will provide more flexibility in retrieving data,
because the time required to read back the
conversion results is shorter.
DATA RETRIEVAL TIME
The available time for retrieving the conversion data
(t_RETRV) from the DDC316 is the difference between
the integration time (t_INT) and the measurement time
(t_MEAS), as shown in Figure 11. Retrieval begins after
DVALID goes low, and must complete before CONV
toggles, for optimal noise performance (see the t_CNDC
timing specification).
Sometimes, it is not possible to retrieve all of the data
in time when using the TDM data output mode; for
example, when integration times are short and DCLK
is slow. In these cases, using the parallel data output
mode will help because the required time for retrieval
decreases by a factor of four.
CONV
DVALID
DCLK
DOUT
t_MEAS
t_INT
t_RETRV
t_CNDC
Figure 11. Data Retrieval Time
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