DDC316_17 Datasheet, PDF (17/28 Pages) Texas Instruments – 16-Channel, Current-Input Analog-to-Digital Converter

DDC316
www.ti.com......................................................................................................................................................... SBAS370A – MARCH 2008 – REVISED APRIL 2009
Writing and Reading of the Configuration Register
Figure 2 shows the timing diagram for writing to and
reading from the configuration register. Writing and
reading must be done before or after CONV toggles.
The data on pin DIN_CFG are latched on the falling
edge of CLK. The first four bits are used as
preamble; only when these bits equal '1010' are the
contents of the following 16 bits loaded into the
configuration register. Once the content is loaded, the
shift register immediately clears so that a new
configuration can be written, if needed. It is
recommended to leave the DIN_CFG pin to logic '0'
when not programming the register.
Once the configuration register updates, it is loaded
into the data shift register to be output on DOUT1.
When DVALID is goes low, the configuration register
is available to be read. If the data are not read back,
then the register is overwritten by the conversion data
on the following conversion. Data are shifted out on
the falling edge of DCLK.
SYSTEM AND DATA CLOCKS (CLK AND
DCLK)
The system clock is supplied to CLK and the data
clock is supplied to DCLK. Make sure the clock
signals are clean; avoid overshoot or ringing. DCLK
should be held low after the data have been shifted
out, or while CONV is transitioning; DCLK should not
be left free-running.
The integration and conversion process is
fundamentally independent of the data retrieval
process. Consequently, the CLK and DCLK
frequencies need not be the same, although for best
performance, it is highly recommended that they be
derived from the same clocking source to keep their
phase relationship constant.
When using multiple DDC316s, pay close attention to
the DCLK distribution on the printed circuit board
(PCB). In particular, make sure to minimize skew in
the DCLK signal because the skew can lead to timing
violations in the serial interface specifications.
DATA VALID (DVALID)
The DVALID signal indicates that data are ready.
Data retrieval may begin after DVALID goes low. This
signal goes low on the rising edge of the system
clock (CLK), and goes high on the first falling edge of
DCLK during the data retrieval process. Data retrieval
from the DDC316 can be done either by polling the
DVALID signal or by counting the number of clock
cycles after a transition of the CONV signal. While
using the counting method, the number of clock
cycles to wait depends on the mode of operation,
either the low power or the high speed mode. The
exact number of CLK cycles to wait for the two
different modes is given in Table 3.
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Product Folder Link(s): DDC316
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